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Solution Manual For Fundamentals of Logic Design, 7th Edition

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    An ’s Solutions Manual to Accompany F UNDAMENTALS OF L OGIC D ESIGN , 7 TH E DITION CHARLES H. ROTH, JR. LARRY L. KINNEY

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    SOLUTIONS MANUAL TO ACCOMPANY FUNDAMENTALS OF LOGIC DESIGN S EVENTH E DITION CHARLES H. ROTH, JR. University of Texas at Austin LARRY L. KINNEY University of Minnesota, Twin Cities

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    iii TABLE OF CONTENTS I. INTRODUCTION 1 1.1 Using the Text in a Lecture Course 1 1.2 Some Remarks About the Text 2 1.3 Using the Text in a Self-Paced Course 2 1.4 Use of Computer Software 4 1.5 Suggested Equipment for Laboratory Exercises 5 II. SOLUTIONS TO HOMEWORK PROBLEMS 7 Unit 1 Problem Solutions 7 Unit 2 Problem Solutions 17 Unit 3 Problem Solutions 23 Unit 4 Problem Solutions 31 Unit 5 Problem Solutions 41 Unit 6 Problem Solutions 57 Unit 7 Problem Solutions 71 Unit 8 Problem Solutions 91 Unit 9 Problem Solutions 97 Unit 10 Problem Solutions 113 Unit 11 Problem Solutions 119 Unit 12 Problem Solutions 125 Unit 13 Problem Solutions 145 Unit 14 Problem Solutions 157 Unit 15 Problem Solutions 177 Unit 16 Problem Solutions 201 Unit 17 Problem Solutions 215 Unit 18 Problem Solutions 229 Unit 19 Problem Solutions 245 Unit 20 Problem Solutions 257 III. SOLUTIONS TO DESIGN, SIMULATION, AND LAB EXERCISES 263 Unit 8 Design Problems 263 Unit 10 Design and Simulation Problems 283 Unit 12 Design and Simulation Problems 297 Unit 16 Design and Simulation Problems 303 Unit 17 Simulation and Lab Problems 313 Unit 20 Lab Design Problems 321 IV. SAMPLE UNIT TESTS 351

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    1 I: INTRODUCTION The text, Fundamentals of Logic Design,7th edition, has been designed so that it can be used either for a standard lecture course or for a self-paced course. The text is divided into 20 study units in such a way that the average study time for each unit is about the same. The units have undergone extensive class testing in a self-paced environment and have been revised based on student feedback. The study guides and text material are sufficient to allow almost all students to achieve mastery of all of the objectives. For example, the material on Boolean algebra and algebraic simplification is 2½ units because students found this topic difficult. There is a separate unit on going from problem statements to state graphs because this topic is difficult for many students. The textbook contains answers for all of the problems that are assigned in the study guides. This ’s Manual contains complete solutions to these problems. Solutions to the remaining homework problems as well as all design and simulation exercises are also included in this manual. In the solutions section of this manual, the abbreviation FLD stands for Fundamentals of Logic Design (7th ed.). Information on the self-paced course as previously taught at the University of Texas using an earlier edition of the textbook is available from Prof. Charles H. Roth, croth@ austin.rr.com . In addition to the textbook and study guides, teaching a self-paced course requires that a set of tests be prepared for each study unit. This manual contains a sample test for each unit. 1.1 Using the Text in a Lecture Course Even though the text was developed in a self-paced environment, the text is well suited for use in a standard lecture course. Since the format of the text differs somewhat from a conventional text, a few suggestions for using the text in a lecture course may be appropriate. Except for the inclusion of objectives and study guides, the units in the text differ very little from chapters in a standard textbook. The study guides contain very basic questions, while the problems at the end of each unit are of a more comprehensive nature. For this reason, we suggest that specific study guide questions be assigned for students to work through on their own before working out homework problems selected from those at the end of the unit. The unit tests given in Part IV of this manual provide a convenient source of additional homework assignments or a source of quiz problems. The text contains many examples that are completely worked out with detailed step-by-step explanations. Discussion of these detailed examples in lecture may not be necessary if the students study them on their own. The lecture time is probably better spent discussing general principles and applications as well as providing help with some of the more difficult topics. Since all of the units have study guides, it would be possible to assign some of the easier topics for self-study and devote the lectures to the more difficult topics. At the University of Texas a class composed largely of Electrical Engineering and Computer Science sophomores and juniors covers 18 units (all units except 6 and 19) of the text in one semester. Units 8, 10, 12, 16, 17, and 20 contain design problems that are suitable for simulation and lab exercises. The design problems help tie together and review the material from a number of preceding units. Units 10, 17, and 20 introduce the VHDL

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    2 hardware description language. These units may be omitted if desired since no other units depend on them. 1.2 Some Remarks About the Text In this text, students are taught how to use Boolean algebra effectively, in contrast with many texts that present Boolean algebra and a few examples of its application and then leave it to the student to figure out how to use it effectively. For example, use of the theorem x + yz = (x + y) (x + z) in factoring and multiplying out expressions is taught explicitly, and detailed guidelines are given for algebraic simplification. Sequential circuits are given proper emphasis, with over half of the text devoted to this subject. The pedagogical strategy the text uses in teaching sequential circuits has proven to be very effective. The concepts of state, next state, etc. are first introduced for individual flip-flops , next for counters, then for sequential circuits with inputs, and finally for more abstract sequential circuit models. The use of timing charts, a subject neglected by many texts, is taught both because it is a practical tool widely used by logic design engineers and because it aids in the understanding of sequential circuit behavior. The most important and often most difficult part of sequential circuit design is formulating the state table or graph from the problem statement, but most texts devote only a few paragraphs to this subject because there is no algorithm. This text devotes a full unit to the subject, presents guidelines for deriving state tables and graphs, and provides programmed exercises that help the student learn this material. Most of the material in the text is treated in a fairly conventional manner with the following exceptions: (1) The diagonal form of the 5-variable Karnaugh map is introduced in Unit 5. (We find that students make fewer mistakes when using the diagonal form of 5- variable map in comparison with the side-by-side form.) Unit 5 also presents a simple algorithm for finding all essential prime implicants from a Karnaugh map. (2) Both the state graph approach (Unit 18) and the SM chart approach (Unit 19) for designing sequential control circuits are presented. (3) The introduction to the VHDL hardware description language in Units 10, 17, and 20 emphasizes the relation between the VHDL code and the actual hardware. 1.3 Using the Text in a Self-Paced Course This section introduces the personalized system of self-paced instruction (PSI) and offers suggestions for using the text in a self-paced course. PSI (Personalized System of Instruction) is one of the most popular and successful systems used for self-paced instruction. The essential features of the PSI method are (a) Students are permitted to pace themselves through the course at a rate commensurate with their ability and available time. (b) A student must demonstrate mastery of each study unit before going onto the next. (c) The written word is stressed; lectures, if used, are only for motivation and not for transmission of critical information. (d) Use of proctors permits repeated testing, immediate scoring, and significant personal interaction with the students. These factors work together to motivate students toward a high level of achievement in a well-

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    3 designed PSI course. The PSI method of instruction and its implementation are described in detail in the following references: 1. Keller, Fred S. and J. Gilmour Sherman, The Keller Plan Handbook , W. A. Benjamin, Inc., 1974. 2. Sherman, J.G., ed., Personalized System of Instruction: 41 Germinal Papers , W. A. Benjamin, Inc., 1974. 3. Roth, C. H., The Personalized System of Instruction – 1962 to 1998 , presented at the 1999 ASEE Annual Conference. (Go to http://search.asee.org and search under Conference Papers for “The Personalized System of Instruction”.) Results of applying PSI to a first course in logic design of digital systems are described in Roth, C.H., Continuing Effectiveness of Personalized Self-Paced Instruction in Digital Systems Engineering , Engineering Education, Vol. 63, No. 6, March 1973. The instructor in charge of a self-paced course will serve as course manager in addition to his role in the classroom. For a small class, he may spend a good part of his time acting as proctor in the classroom, but as class size increases he will have to devote more of his time to supervision of course activities and less time to individual interaction with students. In his managerial role, the instructor is responsible for organizing the course, selection and training of proctors, supervision of proctors, and monitoring of student progress. The proctors play an important role in the success of a self-paced course, and therefore their selection, training, and supervision is very important. After an initial session to discuss proper ways of grading readiness tests and interacting with students, weekly proctor meetings to discuss course procedures and problems may be appropriate. A progress chart showing the units completed by each student is very helpful in monitoring student progress through the course. The instructor may wish to have individual conferences with students who fall too far behind. The instructor needs to be available in the classroom to answer individual student questions and to assist with grading of readiness tests as needed. He should make a special point to speak with the weak or slow students and give them a word of encouragement. From time to time he may need to settle differences which arise between proctors and students. Various strategies for organizing a PSI course are described in the Keller Plan Handbook . The procedures previously used for operating the self-paced digital logic course at the University of Texas are described in “Unit 0”, which is available from Prof. Charles H. Roth, .croth@austin.rr.com . At the first class meeting, we handed out a copy of Unit 0. The students were asked to read through Unit 0 and take a short test on the course procedures. This test was immediately evaluated so that the student could complete Unit 0 before the end of the first class period. In this way, the student was exposed to the basic way the course operated and was ready to proceed immediately with Unit 1 in the textbook. During a typical class period, some of the students spent their time studying but most of the students came prepared to take a unit test. At the beginning of the period, the instructor or a proctor was available to answer student questions on an individual basis. Later in the

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    4 period, most of the time was spent evaluating unit tests. We found that a standard 50 minute class period was not long enough for a PSI session. We usually scheduled sessions of 1½ or 2 hours or longer depending on class size. This allowed adequate time for students to have their questions answered, take a unit test, and have their tests graded. Interactive grading of the tests with the student present is an important part of the PSI system and adequate time must be allowed for this activity. If you have a large number of students and proctors, you may wish to prepare a manual for guidance of your proctors. The procedures that we used for evaluating unit tests are described in a Proctor’s Manual, which can be obtained by writing to Professor Charles H. Roth. 1.4. Use of Computer Software Three software packages are included on the CD that accompanies the textbook. The first is a logic simulator program called SimUaid , the second is a basic computer-aided logic design program called LogicAid , and the third is a VHDL Simulator called DirectVHDL . In addition, we use the Xilinx ISE software for synthesizing VHDL code and downloading to CPLD or FPGA circuit boards. The Xilinx ISE software is available at nominal cost through the Xilinx University Program (for information, go to www.xilinx.com/university/index.htm). A “Webpack” version of the Xilinx software is also available for downloading from the Xilinx.com website. SimUaid provides an easy way for students to test their logic designs by simulating them. We first introduce SimUaid in Unit 4, where we ask the students to design a simple logic circuit such as problem 4.13 or 4.14, and simulate it. SimUaid is easy to learn, and it is highly interactive so that students can flip a simulated switch and immediately observe the result. In Unit 8, students design a multiple-output combinational logic circuit using NAND and NOR gates and test its operation using SimUaid . Students can use the simulator to help them understand the operation of latches and flip-flops in Unit 11. In Unit 12, we ask them to design a counter and simulate it (one part of problem 12.10). In Unit 16, students use SimUaid to test their sequential circuit designs. They can also generate VHDL code from their SimUaid circuit, synthesize it, and download it to a circuit board for hardware testing. In Unit 18, students can use the advanced features of SimUaid to simulate a multiplier or divider controlled by a state machine. LogicAid provides an easy way to introduce students to the use of the computer in the logic design process. It enables them to solve larger, more practical design problems than they could by hand. They can also use LogicAid to verify solutions that they have worked out by hand. Instructors can use the program for grading homework and quizzes. We first introduce LogicAid in Unit 5. The program has a Karnaugh Map Tutorial mode that is very useful in teaching students to solve Karnaugh map problems. This tutorial mode helps students learn to derive minimum solutions from a Karnaugh map by informing them at each step whether that step is correct or not. It also forces them to choose essential prime implicants first. When in the KMap tutor mode, LogicAid prints “KMT” at the top of each output page, so you can check to see if the problems were actually solved in the tutorial mode. Students can use LogicAid to help them solve design problems in Units 8, 16, 18, 19 and other units. For designing sequential circuits, they can input a state graph, convert it to a state table, reduce the state table, make a state assignment, and derive minimized logic equations for outputs and flip-flop inputs. The LogicAid State Table Checker is useful for Units 14 and 16, and for other units in which students construct state tables. It allows students to check their solutions without revealing the correct

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    5 answers. If the solution is wrong, the program displays a short input sequence for which the student’s table fails. The LogicAid folder on the CD contains encoded copies of solutions for most of the state graph problems in Fundamentals of Logic Design, 7th Ed . If you wish to create a password-protected solution file for other state table problems, enter the state table into LogicAid , syntax check it, and then hold down the Ctrl key while you select Save As on the file menu. The Partial Graph Checker serves as a state graph tutor that allows a student to check his work at each step while constructing a state graph. If the student makes a mistake, it provides feedback so that the student can correct his answer. The partial graph checker works with any state graph problem for which an encoded state table solution file is provided. The DirectVHDL simulator helps students learn VHDL syntax because it provides immediate visual feedback when they make mistakes. Our students use it for simulating VHDL code in Units 10, 17, and 20. Students can simulate and debug their code at home and then bring the code into lab for synthesis and hardware testing. 1.5. Suggested Equipment for Laboratory Exercises Many types of logic lab equipment are available that are adequate to perform the lab exercises. Since most logic design is done today using programmable logic instead of individual ICs, we now recommend use of CPLDs or FPGAs for hardware implementation of logic circuit designs. At the University of Texas, we are presently using the XILINX Spartan-3 FPGA boards, which are available from Digilent. The Spartan-3 FPGA has more than an adequate number of logic cells to implement the lab exercises in the text. The board has 8 switches, 4 pushbuttons, 8 single LEDs, and four 7-segment LEDs.. Information about this board and other CPLD and FPGA boards made by Digilent can be found on their website, www.digilentinc.com . We use the board in conjunction with the Xiliinx ISE software mentioned earlier.

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    6

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    Unit 1 Solutions 7 II. SOLUTIONS TO HOMEWORK PROBLEMS Unit 1 Problem Solutions 757.25 10 16 | 757 0.25 16 | 47 r5 16 16 | 2 r15=F 16 (4).00 0 r2 ∴ 757.25 10 = 2F5.40 16 = 0010 1111 0101 . 0100 0000 2 2 F 5 4 0 1.1 (a) 123.17 10 16 | 123 0.17 16 | 7 r11 16 0 r7 (2).72 16 (11).52 16 (8).32 ∴ 123.17 10 = 7B.2B 16 = 0111 1011 . 0010 1011 2 7 B 2 B 356.89 10 16 | 356 0.89 16 | 22 r4 16 16 | 1 r6 (14).24 0 r1 16 (3).84 16 (13).44 16 (7).04 ∴ 356.89 10 = 164.E3 16 = 0001 0110 0100 . 1110 0011 2 1 6 4 E 3 1.1 (c) 1063.5 10 16 | 1063 0.5 16 | 66 r7 16 16 | 4 r2 (8).00 0 r4 ∴ 1063.5 10 = 427.8 16 = 0100 0010 0111 . 1000 2 4 2 7 8 EB1.6 16 = E × 16 2 + B × 16 1 + 1 × 16 0 + 6 × 16 –1 = 14 × 256 + 11 × 16 + 1 + 6/16 = 3761.375 10 1110 1011 0001 . 011(0) 2 E B 1 6 7261.3 8 = 7 × 8 3 + 2 × 8 2 + 6 × 8 1 + 1 + 3 × 8 –1 = 7 × 512 + 2 × 64 + 6 × 8 + 1 + 3/8 = 3761.375 10 111 010 110 001 . 011 8 7 2 6 1 3 1.2 (a) 59D.C 16 = 5 × 16 2 + 9 × 16 1 + D × 16 0 + C × 16 –1 = 5 × 256 + 9 × 16 + 13 + 12/16 = 1437.75 10 0101 1001 1101 . 1100 16 5 9 D C 2635.6 8 = 2 × 8 3 + 6 × 8 2 + 3 × 8 1 + 5 × 8 0 + 6 × 8 –1 = 2 × 512 + 6 × 64 + 3 × 8 + 5 + 6/8 = 1437.75 10 010 110 011 101 . 110 8 2 6 3 5 6 1.1 (b) 1.1 (d) 1.2 (b) 3BA.25 14 = 3 × 14 2 + 11 × 14 1 + 10 × 14 0 + 2 × 14 –1 + 5 ×14 –2 = 588 + 154 + 10 + 0.1684 = 752.1684 10 6 | 752 0.1684 6 | 125 r2 6 6 | 20 r5 (1).0104 6 | 3 r2 6 0 r3 (0).0624 6 (0).3744 6 (2).2464 6 (1).4784 ∴ 3BA.25 14 = 752.1684 10 = 3252.1002 6 1.3 1457.11 10 16 | 1457 0.11 16 | 91 r1 16 16 | 5 r11=B 16 (1).76 0 r5 16 (12).16 ∴ 1457.11 10 = 5B1.1C 16 5B1.1C 16 = 11 23 01 . 01 30 4 5 B 1 1 C 5 B 1 1 C 5B1.1C 16 = 010110110001.00011100 2 =2661.070 8 2 6 6 1 0 7 0 DEC.A 16 = D × 16 2 + E × 16 1 + C × 16 0 + A× 16 –1 = 3328 + 224 + 12 + 0.625 =3564.625 10 1.4 (b) 1.4 (c) 1.4 (d)

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    Unit 1 Solutions 8 1.12 (c) A52.A4 11 = 10 × 121 + 5 × 11 + 2 + 10/11 + 4/121 = 1267.94 10 9 | 1267 0.94 9 | 140 r7 9 9 | 15 r5 (8).46 9 | 1 r6 9 0 r1 (4).14 ∴ A52.A4 11 = 1267.94 10 = 1657.8427 9 ... 1305.375 10 16 | 1305 0.375 16 | 81 r9 16 5 r1 (6).000 ∴ 1305.375 10 = 519.600 16 = 0101 0001 1001 . 0110 0000 0000 2 5 1 9 6 0 0 1644.875 10 16 | 1644 0.875 16 | 102 r12 16 6 r6 (14).000 ∴ 1644.875 10 = 66C.E00 16 = 0110 0110 1100 . 1110 0000 0000 2 6 6 C E 0 0 1.10 (a) 1.10 (c) 1.5 (a) 1 1 1 1111 (Add) + 1010 11001 1111 (Sub) − 1010 0101 1111 (Multiply) ×1010 0000 1111 11110 0000 011110 1111 10010110 See FLD p. 730 for solutions. 101 111 010 100.101 2 = 5724.5 8 = 5 × 8 3 + 7 × 8 2 + 2 × 8 1 + 4 × 8 0 + 5 × 8 –1 = 5 × 512 + 7 × 64 + 2 × 8 + 4 + 5/8 = 3028.625 10 1011 1101 0100.1010 2 = BD4.A 16 B × 16 2 + D × 16 1 + 4 × 16 0 + A × 16 –1 11 × 256 + 13 × 16 + 4 + 10/16 = 3028.625 10 1.11 (a) 375.54 8 = 3 × 64+ 7 × 8 + 5 + 5/8 + 4/64 = 253.6875 10 3 | 253 0.69 3 | 84 r1 3 3 | 28 r0 (2).07 3 | 9 r1 3 3 | 3 r0 (0).21 3 | 1 r0 3 0 r1 (0).63 3 (1).89 ∴ 375.54 8 = 100101.2001 3 301.12 10 16 | 301 0.12 16 | 18 r13 16 1 r2 (1).92 16 (14).72 ∴ 301.12 10 = 12D.1E 16 = 0001 0010 1101 . 0001 1110 2 1 2 D 1 E 11.33 10 16 | 111 0.33 6 r15 = F 16 16 (5).28 16 (4).48 ∴ 111.33 10 = 6F.54 16 = 0110 1111 . 0101 0100 2 6 F 5 4 100 001 101 111.010 2 = 4157.2 8 = 4 × 8 3 + 1 × 8 2 5 × 8 1 + 7 × 8 0 + 2 × 8 –1 = 4 × 512 + 1 × 64 + 5 × 8 + 7 + 2/8 = 2159.25 10 1000 0110 1111.0100 2 = 86F.4 16 = 8 × 16 2 + 6 × 16 1 + F × 16 0 × 4 × 16 –1 = 8 × 256 + 6 × 16 + 15 + 4/16 = 2159.25 10 384.74 10 4 | 384 0.74 4 | 96 r0 4 4 | 24 r0 (2).96 4 | 6 r0 4 4 | 1 r2 (3).84 0 r1 4 (3).36 ∴ 384.74 10 = 12000.233113 4 ... 1.12 (a) 1.6, 1.7, 1.8, 1.9 1.5 (b, c) See FLD p. 730 for solutions. 1.10 (b) 1.10 (d) 1.11 (b) 1.12 (b)

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    Unit 1 Solutions 9 3 | 97 .7 3 |32 r1 3 3 |10 r2 (2).1 3 |3 r1 3 3 |1 r0 (0).3 0 r1 3 (0).9 3 (2).7 ∴ 97.7 10 = 10121.2002.... 3 1110212.20211 3 01 11 02 12.20 21 10 = 1425.673 9 Base 3 Base 9 00 0 01 1 02 2 10 3 11 4 12 5 20 6 21 7 22 8 544.1 9 = 5 × 9 2 + 4 × 9 1 + 4 × 9 0 + 1 × 9 –1 = 5 × 81 + 4 × 9 + 4 + 1/9 = 445 1/9 10 16 | 445 1/9 16 | 27 r13 16 16 | 1 r11 (1)7/9 0 r1 16 (12)4/9 16 (7)1/9 ∴ 544.1 9 = 1BD.1C7 16 = 1 1011 1101.0001 1100 0111 2 ... 1.13 1.15 (c) 16 | 97 .7 16 | 6 r1 16 0 r6 (11).2 16 (3).2 ∴ 97.7 10 = 61.B3333.... 16 (a) 61.B3333.. 16 = 110 0001.1011 0011 0011 0011 0011... 2 (b) 1 100 001.101 100 110 011 001 100 11... 2 = 141.5 4631 4631.... 8 1.14 (a), (b), (c) 1.14 (d) 5 | 97 .7 5 |19 r2 5 5 |3 r4 (3).5 0 r3 5 (2).5 ∴ 97.7 10 = 342.322.. 5 1.14 (e) 2983 63/64 10 = 8 | 2983 0.984 8 | 372 r7 8 8 | 46 r4 (7).872 9 | 5 r6 8 0 r5 (6).976 ∴ 2983 63/64 10 = 5647.76 8 (or 5647.77 8 ) = 101 110 100 111.111 110 2 (or 101 110 100 111.111 111 2) 1.16 (a) 93.70 10 8 | 93 0.70 8 | 11 r5 8 8 | 1 r3 (5).60 0 r1 8 (4).80 ∴ 93.70 10 = 135.54 8 = 001 011 101.101 100 2 1.16 (b) 1900 31/32 10 8 | 1900 0.969 8 | 273 r4 8 8 | 29 r5 (7).752 9 | 3 r5 8 0 r3 (6).016 ∴ 1900 31/32 10 = 3554.76 8 = 011 101 101 100.111 110 2 109.30 10 8 | 109 0.30 8 | 13 r5 8 8 | 1 r5 (2).40 0 r1 8 (3).20 ∴ 109.30 10 = 155.23 8 = 001 101 101.010 011 2 1.16 (c) 1.16 (d)

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    Unit 1 Solutions 10 11011 Quotient 1110 )110000001 1110 10100 1110 11000 1110 10101 1110 111 Remainder 1 1 1 1 1 110010 (Add) 110010 (Sub) 11101 11101 1001111 10101 110010 (Mult) 11101 110010 000000 0110010 110010 11111010 110010 1010001010 110010 10110101010 1 1 1 1 1 (a) 10100100 (b) 10010011 01110011 01011001 0110001 00111010 1 1 (c) 11110011 10011110 01010101 10111 Quotient 110 )10001101 110 1011 110 1010 110 1001 110 11 Remainder 1.17(c) 101110 Quotient 101 )11101001 101 1001 101 1000 101 110 101 11 Remainder 1100 Quotient 1001 )1110010 1001 1010 1001 110 Remainder 1 1 1 1 1 1 1111 (Add) 1111 (Subtract) 1001 1001 11000 0110 1111 (Multiply) 1001 1111 0000 01111 0000 001111 1111 10000111 1 1 1 1 1 1101001(Add) 1101001 (Sub) 110110 110110 10011111 110011 1101001 (Mult) 110110 0000000 1101001 11010010 1101001 1001110110 0000000 1001110110 1101001 100100000110 1101001 1011000100110 1.17 (a) 1.17 (b) 1.18 1.19(a) 1.19(b) 1.19(c) 1.20(a)

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    Unit 1 Solutions 11 (a) 4 + 3 is 10 in base 7, i.e., the sum digit is 0 with a carry of 1 to the next column. 1 + 5 + 4 is 10 in base 7. 1 + 6 + 0 is 10 in base 7. This overflows since the correct sum is 1000 7 . (b) 4 + 3 + 3 + 3 = 13 in base 10 and 23 in base 5. Try base 10. 1 + 2 + 4 + 1 + 3 = 11 in base 10 so base 10 does not produce a sum digit of 2. Try base 5. 2 + 2 + 4 + 1 + 3 = 22 in base 5 so base 5 works. (c) 4 + 3 + 3 + 3 = 31 in base 4, 21 in base 6, and 11 in base 12. Try base 12. 1 + 2 + 4 + 1 + 3 = B in base 12 so base 12 does not work. Try base 4. 3 + 2 + 4 + 1 + 3 = 31 in base 4 so base 4 does not work. Try base 6. 2 + 2 + 4 + 1 + 3 = 20 so base 6 is correct. 1.21 If the binary number has n bits (to the right of the radix point), then its precision is (1/2 n+1 ). So to have the same precision, n must satisfy (1/2 n+1 ) < (1/2)(1/10 4 ) or n > 4/(log 2) = 13.28 so n must be 14. 1.22 .363636.... = (36/10 2 )(1 + 1/10 2 + 1/10 4 + 1/10 6 + …) = (36/10 2 )[1/(1 – 1/10 2 )] = (36/10 2 )[10 2 /99] = 36/99 = 4/11 8(4/11) = 2 + 10/11 8(10/11) = 7 + 3/11 8(3/11) = 2 + 2/11 8(2/11) = 1 + 5/11 8(5/11) =3 + 7/11 8(7/11) = 5+ 1/11 8(1/11) = 0 + 8/11 8(8/11) = 5 + 9/11 8(9/11) = 6 + 6/11 8(6/11) = 4 + 4/11 8(4/11) = 2 + 10/11 Repeats: .27213505642……. 1.23 Expand the base b number into a power series N = d 3k-1 b 3k-1 + d 3k-2 b 3k-2 + d 3k-3 b 3k-3 + …. + d 5 b 5 + d 4 b 4 + d 3 b 3 + d 2 b 2 + d 1 b 1 + d 0 b 0 + d -1 b -1 + d -2 b -2 + d -3 b -3 + …. + d -3m+2 b -3m+2 + d -3m+1 b -3m+1 + d -3m b -3m where each d i has a value from 0 to (b-1). (Note that 0’s can be appended to the number so that it has a multiple of 3 digits to the left and right of the radix point.) Factor b 3 from each group of 3 consecutive digits of the number to obtain N = ( d 3k-1 b 2 + d 3k-2 b 1 + d 3k-3 b 0 ) (b 3 ) (k-1) + …. + (d 5 b 2 + d 4 b 1 + d 3 b 0 ) (b 3 ) 1 + (d 2 b 2 + d 1 b 1 + d 0 b 0 ) (b 3 ) 0 + (d -1 b 2 + d -2 b 1 + d -3 b 0 ) (b 3 ) -1 + …. + (d -3m+2 b 2 + d -3m+1 b 1 + d -3m b 0 )(b 3 ) -m Each (d 3i-1 b 2 + d 3i-2 b 1 + d 3i-3 b 0 ) has a value from 0 to [(b-1)b 2 + (b-1)b 1 + (b-1)b 0 ] = (b-1)( b 2 + b 1 + b 0 ) = (b 3 -1) so it is a valid digit in a base b 3 number. Consequently, the last expression is the power series expansion for a base b 3 number. 1.24 (a) Expand the base b 3 number into a power series N = d k (b 3 ) k + d k-1 (b 3 ) k-1 + … + d 1 (b 3 ) 1 + d 0 (b 3 ) 0 + d -1 (b 3 ) -1 + …. + d -m (b 3 ) -m where each d i has a value from 0 to (b 3 -1). Consequently, d i can be represented as a base b number in the form (e 3i-1 b 2 + e 3i-2 b 1 + e 3i-3 b 0 ) Where each e j has a value from 0 to (b-1). Substituting these expressions for the d i produces a power series expansion for a base b number. 1.24 (b) 1011 Quotient 1010 )1110100 1010 10010 1010 10000 1010 110 Remainder 100011 Quotient 1011 )110000011 1011 10001 1011 1101 1011 10 Remainder 1.20(b) 1.20(c) (5 - 1) = 4 5 , (5 2 - 1) = 44 5 and (5 3 - 1) = 444 5 (b n -1) = (b - 1)(b n-1 ) + b n-1 = (b - 1)b n-1 + (b - 1)b n-2 + b n-2 = (b - 1)b n-1 + (b - 1)b n-2 + … + (b - 1)b + (b - 1) This expression is the polynomial expansion for the base b number with n digits (b - 1)(b - 1) … (b - 1) 1.25(a) 1.25(b) 1.26(a) (b + 1) 2 = b 2 + 2b + 1 so (11 b ) 2 = 121 b if b > 2. (b 2 + b + 1) 2 = b 4 + 2b 3 + 3b 2 + 2b + 1 so (111 b ) 2 = 12321 b if b > 3. (b 2 + 2b + 1) 2 = b 4 + 4b 3 + 6b 2 + 4b + 1 so (121 b ) 2 = 14641 b if b > 6. (b 3 + b 2 + b + 1) 2 = b 6 + 2b 5 + 3b 4 + 4b 3 + 3b 2 + 2b + 1 so (1111 b ) 2 = 1234321 b if b > 4. 1.26(b) 1.26(c) 1.26(d)

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    Unit 1 Solutions 12 Alternate Solutions: 6 2 2 1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 1 0 5 0 1 1 1 6 1 0 0 0 7 1 0 0 1 8 1 0 1 0 9 1 0 1 1 1100 0011 = 83 (0100) (0101) (1100) (1101) Alternate Solutions: 5 2 2 1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 1 0 5 1 0 0 0 6 1 0 0 1 7 1 0 1 0 8 1 0 1 1 9 1 1 1 0 1110 0110 = 94 (0100) (0101) (1100) (1101) 1.31 1.32 Alternate Solutions: 7 3 2 1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 A 1 1 0 0 B 1 1 0 1 (0011) (1011) 1.33 B4A9 = 1101 0101 1100 1010 Alt.: = " " 1011 " (a) 8 4 -2 -1 0 0 0 0 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 1 4 0 1 0 0 5 1 0 1 1 6 1 0 1 0 7 1 0 0 1 8 1 0 0 0 9 1 1 1 1 (b) The 9’s complement of a decimal number represented with this weighted code can be obtained by replacing 0's with 1's and 1's with 0's (bit-by-bit complement). 1.34 4 3 2 1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 1 0 0 4 1 0 0 0 5 1 0 0 1 6 1 0 1 0 7 1 1 0 0 8 1 1 0 1 9 1 1 1 0 9154 = 1110 0001 1001 1000 1.28 5-3-1-1 is possible, but 6-4-1-1 is not, because there is no way to represent 3 or 9. Alternate Solutions: 5 3 1 1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 1 0 0 0 6 1 0 0 1 7 1 0 1 1 8 1 1 0 0 9 1 1 0 1 5-4-1-1 is not possible, because there is no way to represent 3 or 8. 6-3-2-1 is possible: 6 3 2 1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 1 0 0 0 7 1 0 0 1 8 1 0 1 0 9 1 1 0 0 1.29 1.30 (0010) (0110) (1010) (1110) 1.27(a) (0.12) 3 = (1/3 + 2/9) 10 = (2/6 + 8/36) 10 = (3/6 + 2/36) 10 = (0.32) 6 (0.375) 10 = (3/8) 10 = (0.3) 8 (a -1 R -1 + a -2 R -2 + ... + a -m R -m )S n will be an integer for every N only if R m divides S n for some n. Hence, each factor of R must be a factor of S, not necessarily the same number of times. For a specific number N, (a -1 R -1 + a -2 R -2 + ... + a -m R -m )S n will be an integer if each factor of R m is a factor of either S n or (a -1 R m-1 + a -2 R m-2 + ... + a -m ) 1.27(b) 1.27(c) 1.27(d)

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