Solution Manual For Fundamentals of Logic Design, 7th Edition

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An’s Solutions Manual to AccompanyFUNDAMENTALSOFLOGICDESIGN,7THEDITIONCHARLES H. ROTH, JR.LARRY L. KINNEY

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SOLUTIONS MANUALTO ACCOMPANYFUNDAMENTALSOFLOGICDESIGNSEVENTHEDITIONCHARLES H. ROTH, JR.UniversityofTexasatAustinLARRY L. KINNEYUniversityofMinnesota,TwinCities

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iiiTABLE OF CONTENTSI. INTRODUCTION11.1 Using the Text in a Lecture Course11.2Some Remarks About the Text21.3 Using the Text in a Self-Paced Course21.4 Use of Computer Software41.5 Suggested Equipment for Laboratory Exercises5II.SOLUTIONS TO HOMEWORK PROBLEMS7Unit 1 Problem Solutions7Unit 2 Problem Solutions17Unit 3 Problem Solutions23Unit 4 Problem Solutions31Unit 5 Problem Solutions41Unit 6 Problem Solutions57Unit 7 Problem Solutions71Unit 8 Problem Solutions91Unit 9 Problem Solutions97Unit 10 Problem Solutions113Unit 11 Problem Solutions119Unit 12 Problem Solutions125Unit 13 Problem Solutions145Unit 14 Problem Solutions157Unit 15 Problem Solutions177Unit 16 Problem Solutions201Unit 17 Problem Solutions215Unit 18 Problem Solutions229Unit 19 Problem Solutions245Unit 20 Problem Solutions257III. SOLUTIONS TO DESIGN, SIMULATION,AND LAB EXERCISES263Unit 8 Design Problems263Unit 10 Design and Simulation Problems283Unit 12 Design and Simulation Problems297Unit 16 Design and Simulation Problems303Unit 17 Simulation and Lab Problems313Unit 20 Lab Design Problems321IV. SAMPLE UNIT TESTS351

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1I: INTRODUCTIONThe text,Fundamentals of Logic Design,7th edition,has been designed so that itcan be used either for a standard lecture course or for a self-paced course. The text is dividedinto 20 study units in such a way that the average study time for each unit is about the same.The units have undergone extensive class testing in a self-paced environment and have beenrevised based on student feedback. The study guides and text material are sufficient to allowalmost all students to achieve mastery of all of the objectives. For example, the material onBoolean algebra and algebraic simplification is 2½ units because students found this topicdifficult. There is a separate unit on going from problem statements to state graphs becausethis topic is difficult for many students.The textbookcontains answers for all of the problems that are assigned in the studyguides. This’s Manualcontains complete solutions to these problems. Solutionsto the remaining homework problems as well as all design and simulation exercises are alsoincluded in this manual. In the solutions section of this manual, the abbreviation FLD standsforFundamentals of Logic Design(7th ed.).Information on the self-paced course as previously taught at the University of Texasusing an earlier edition of the textbook is available from Prof. Charles H. Roth,croth@austin.rr.com.In addition to the textbook and study guides, teaching a self-paced courserequires that a set of tests be prepared for each study unit. This manual contains a sampletest for each unit.1.1 Using the Text in a Lecture CourseEven though the text was developed in a self-paced environment, the text is wellsuited for use in a standard lecture course. Since the format of the text differs somewhatfrom a conventional text, a few suggestions for using the text in a lecture course may beappropriate. Except for the inclusion of objectives and study guides, the units in the textdiffer very little from chapters in a standard textbook. The study guides contain very basicquestions, while the problems at the end of each unit are of a more comprehensive nature.For this reason, we suggest that specific study guide questions be assigned for students towork through on their own before working out homework problems selected from thoseat the end of the unit. The unit tests given in Part IV of this manual provide a convenientsource of additional homework assignments or a source of quiz problems. The text containsmany examples that are completely worked out with detailed step-by-step explanations.Discussion of these detailed examples in lecture may not be necessary if the students studythem on their own. The lecture time is probably better spent discussing general principlesand applications as well as providing help with some of the more difficult topics. Since allof the units have study guides, it would be possible to assign some of the easier topics forself-study and devote the lectures to the more difficult topics.At the University of Texas a class composed largely of Electrical Engineering andComputer Science sophomores and juniors covers 18 units (all units except 6 and 19) ofthe text in one semester. Units 8, 10, 12, 16, 17, and 20 contain design problems that aresuitable for simulation and lab exercises. The design problems help tie together and reviewthe material from a number of preceding units. Units 10, 17, and 20 introduce the VHDL

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2hardware description language. These units may be omitted if desired since no other units dependon them.1.2Some Remarks About the TextIn this text, students are taught how to use Boolean algebra effectively, in contrast withmany texts that present Boolean algebra and a few examples of its application and then leave it tothe student to figure out how to use it effectively. For example, use of the theorem x + yz = (x + y)(x + z) in factoring and multiplying out expressions is taught explicitly, and detailed guidelines aregiven for algebraic simplification.Sequential circuits are given proper emphasis, with over half of the text devoted to thissubject. The pedagogical strategy the text uses in teaching sequential circuits has proven to be veryeffective. The concepts of state, next state, etc. are first introduced for individual flip-flops,nextfor counters, then for sequential circuits with inputs, and finally for more abstract sequential circuitmodels. The use of timing charts, a subject neglected by many texts, is taught both because it isa practical tool widely used by logic design engineers and because it aids in the understanding ofsequential circuit behavior.The most important and often most difficult part of sequential circuit design is formulatingthe state table or graph from the problem statement, but most texts devote only a few paragraphsto this subject because there is no algorithm. This text devotes a full unit to the subject, presentsguidelines for deriving state tables and graphs, and provides programmed exercises that help thestudent learn this material. Most of the material in the text is treated in a fairly conventionalmanner with the following exceptions:(1)The diagonal form of the 5-variable Karnaugh map is introduced in Unit 5. (We findthat students make fewer mistakes when using the diagonal form of 5-variable map incomparison with the side-by-side form.) Unit 5 also presents a simple algorithm for findingall essential prime implicants from a Karnaugh map.(2)Both the state graph approach (Unit 18) and the SM chart approach (Unit 19) for designingsequential control circuits are presented.(3)The introduction to the VHDL hardware description language in Units 10, 17, and 20emphasizes the relation between the VHDL code and the actual hardware.1.3 Using the Text in a Self-Paced CourseThis section introduces the personalized system of self-paced instruction (PSI) and offerssuggestions for using the text in a self-paced course. PSI (Personalized System of Instruction)is one of the most popular and successful systems used for self-paced instruction. The essentialfeatures of the PSI method are(a)Students are permitted to pace themselves through the course at a rate commensurate withtheir ability and available time.(b)A student must demonstrate mastery of each study unit before going onto the next.(c)The written word is stressed; lectures, if used, are only for motivation and not fortransmission of critical information.(d)Use of proctors permits repeated testing, immediate scoring, and significant personalinteraction with the students.These factors work together to motivate students toward a high level of achievement in a well-

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3designed PSI course.The PSI method of instruction and its implementation are described in detail in the followingreferences:1. Keller, Fred S. and J. Gilmour Sherman,The Keller Plan Handbook, W. A. Benjamin, Inc.,1974.2.Sherman, J.G., ed.,Personalized System of Instruction: 41 Germinal Papers, W. A.Benjamin, Inc., 1974.3. Roth, C. H.,The Personalized System of Instruction – 1962 to 1998, presented at the 1999ASEE Annual Conference. (Go tohttp://search.asee.organd search under ConferencePapers for “The Personalized System of Instruction”.)Results of applying PSI to a first course in logic design of digital systems are described inRoth, C.H.,Continuing Effectiveness of Personalized Self-Paced Instruction in Digital SystemsEngineering, Engineering Education, Vol. 63, No. 6, March 1973.The instructor in charge of a self-paced course will serve as course manager in addition tohis role in the classroom. For a small class, he may spend a good part of his time acting as proctorin the classroom, but as class size increases he will have to devote more of his time to supervisionof course activities and less time to individual interaction with students. In his managerial role, theinstructor is responsible for organizing the course, selection and training of proctors, supervisionof proctors, and monitoring of student progress. The proctors play an important role in the successof a self-paced course, and therefore their selection, training, and supervision is very important.After an initial session to discuss proper ways of grading readiness tests and interacting withstudents, weekly proctor meetings to discuss course procedures and problems may be appropriate.A progress chart showing the units completed by each student is very helpful inmonitoring student progress through the course. The instructor may wish to have individualconferences with students who fall too far behind. The instructor needs to be available in theclassroom to answer individual student questions and to assist with grading of readiness testsas needed. He should make a special point to speak with the weak or slow students and givethem a word of encouragement. From time to time he may need to settle differences whicharise between proctors and students.Various strategies for organizing a PSI course are described in theKeller PlanHandbook. The procedures previously used for operating the self-paced digital logic courseat the University of Texas are described in “Unit 0”, which is available from Prof. Charles H.Roth,.croth@austin.rr.com. At the first class meeting, we handed out a copy of Unit 0. Thestudents were asked to read through Unit 0 and take a short test on the course procedures.This test was immediately evaluated so that the student could complete Unit 0 before theend of the first class period. In this way, the student was exposed to the basic way the courseoperated and was ready to proceed immediately with Unit 1 in the textbook.During a typical class period, some of the students spent their time studying but mostof the students came prepared to take a unit test. At the beginning of the period, the instructoror a proctor was available to answer student questions on an individual basis. Later in the

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4period, most of the time was spent evaluating unit tests. We found that a standard 50 minuteclass period was not long enough for a PSI session. We usually scheduled sessions of 1½ or2 hours or longer depending on class size. This allowed adequate time for students to havetheir questions answered, take a unit test, and have their tests graded. Interactive grading ofthe testswith the student present is an important part of the PSI system and adequate timemust be allowed for this activity. If you have a large number of students and proctors, youmay wish to prepare a manual for guidance of your proctors. The procedures that we used forevaluating unit tests are described in a Proctor’s Manual, which can be obtained by writingto Professor Charles H. Roth.1.4. Use of Computer SoftwareThree software packages are included on the CD that accompanies the textbook. The firstis a logic simulator program calledSimUaid, the second is a basic computer-aided logic designprogram calledLogicAid, and the third is a VHDL Simulator calledDirectVHDL. In addition, weuse the Xilinx ISE software for synthesizing VHDL code and downloading to CPLD or FPGA circuitboards. The Xilinx ISE software is available at nominal cost through the Xilinx University Program(for information, go to www.xilinx.com/university/index.htm). A “Webpack” version of the Xilinxsoftware is also available for downloading from the Xilinx.com website.SimUaidprovides an easy way for students to test their logic designs by simulating them.We first introduceSimUaidin Unit 4, where we ask the students to design a simple logic circuit suchas problem 4.13 or 4.14, and simulate it.SimUaidis easy to learn, and it is highly interactive so thatstudents can flip a simulated switch and immediately observe the result. In Unit 8, students design amultiple-output combinational logic circuit using NAND and NOR gates and test its operation usingSimUaid. Students can use the simulator to help them understand the operation of latches and flip-flopsin Unit 11. In Unit 12, we ask them to design a counter and simulate it (one part of problem 12.10). InUnit 16, students useSimUaidto test their sequential circuit designs. They can also generate VHDLcode from theirSimUaidcircuit, synthesize it, and download it to a circuit board for hardware testing.In Unit 18, students can use the advanced features ofSimUaidto simulate a multiplier or dividercontrolled by a state machine.LogicAidprovides an easy way to introduce students to the use of the computer in the logicdesign process. It enables them to solve larger, more practical design problems than they could byhand. They can also useLogicAidto verify solutions that they have worked out by hand. Instructorscan use the program for grading homework and quizzes. We first introduceLogicAidin Unit 5. Theprogram has a Karnaugh Map Tutorial mode that is very useful in teaching students to solve Karnaughmap problems. This tutorial mode helps students learn to derive minimum solutions from a Karnaughmap by informing them at each step whether that step is correct or not. It also forces them to chooseessential prime implicants first. When in the KMap tutor mode,LogicAidprints “KMT” at the top ofeach output page, so you can check to see if the problems were actually solved in the tutorial mode.Students can useLogicAidto help them solve design problems in Units 8, 16, 18, 19 and otherunits. For designing sequential circuits, they can input a state graph, convert it to a state table, reducethe state table, make a state assignment, and derive minimized logic equations for outputs and flip-flopinputs.TheLogicAidState Table Checker is useful for Units 14 and 16, and for other units in whichstudents construct state tables. It allows students to check their solutions without revealing the correct

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5answers. If the solution is wrong, the program displays a short input sequence for which the student’stable fails. TheLogicAidfolder on the CD contains encoded copies of solutions for most of the stategraph problems inFundamentals of Logic Design, 7th Ed. If you wish to create a password-protectedsolution file for other state table problems, enter the state table intoLogicAid, syntax check it, andthen hold down the Ctrl key while you select Save As on the file menu. The Partial Graph Checkerserves as a state graph tutor that allows a student to check his work at each step while constructinga state graph. If the student makes a mistake, it provides feedback so that the student can correct hisanswer. The partial graph checker works with any state graph problem for which an encoded state tablesolution file is provided.The DirectVHDL simulator helps students learn VHDL syntax because it provides immediatevisual feedback when they make mistakes. Our students use it for simulating VHDL code in Units 10,17, and 20. Students can simulate and debug their code at home and then bring the code into lab forsynthesis and hardware testing.1.5. Suggested Equipment for Laboratory ExercisesMany types of logic lab equipment are available that are adequate to perform the labexercises. Since most logic design is done today using programmable logic instead of individualICs, we now recommend use of CPLDs or FPGAs for hardware implementation of logic circuitdesigns. At the University of Texas, we are presently using the XILINX Spartan-3 FPGA boards,which are available from Digilent. The Spartan-3 FPGA has more than an adequate number oflogic cells to implement the lab exercises in the text. The board has 8 switches, 4 pushbuttons, 8single LEDs, and four 7-segment LEDs.. Information about this board and other CPLD and FPGAboards made by Digilent can be found on their website,www.digilentinc.com. We use the boardin conjunction with the Xiliinx ISE software mentioned earlier.

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Unit 1 Solutions7II. SOLUTIONS TO HOMEWORK PROBLEMSUnit 1 Problem Solutions757.251016| 7570.2516| 47r51616| 2r15=F16(4).000r2∴757.2510= 2F5.4016=001011110101.0100000022F5401.1 (a)123.171016| 1230.1716| 7r11160r7(2).7216(11).5216(8).32∴123.1710= 7B.2B16=01111011.0010101127B2B356.891016| 3560.8916| 22r41616| 1r6(14).240r116(3).8416(13).4416(7).04∴356.8910= 164.E316=000101100100.111000112164E31.1 (c)1063.51016| 10630.516| 66r71616| 4r2(8).000r4∴1063.510= 427.816=010000100111.100024278EB1.616= E × 162+ B × 161+ 1 × 160+ 6 × 16–1= 14 × 256 + 11 × 16 + 1 + 6/16 = 3761.37510111010110001.011(0)2EB167261.38= 7 × 83+ 2 × 82+ 6 × 81+ 1 + 3 × 8–1= 7 × 512 + 2 × 64 + 6 × 8 + 1 + 3/8 = 3761.37510111010110001.0118726131.2 (a)59D.C16= 5 × 162+ 9 × 161+ D × 160+ C × 16–1= 5 × 256 + 9 × 16 + 13 + 12/16 =1437.7510010110011101.11001659DC2635.68= 2 × 83+ 6 × 82+ 3 × 81+ 5 × 80+ 6 × 8–1= 2 × 512 + 6 × 64 + 3 × 8 + 5 + 6/8 =1437.7510010110011101.1108263561.1 (b)1.1 (d)1.2 (b)3BA.2514= 3 × 142+ 11 × 141+ 10 × 140+ 2 × 14–1+ 5×14–2= 588 + 154 + 10 + 0.1684 = 752.1684106| 7520.16846| 125r266| 20r5(1).01046| 3r260r3(0).06246(0).37446(2).24646(1).4784∴3BA.2514= 752.168410= 3252.100261.31457.111016| 14570.1116| 91r11616| 5r11=B16(1).760r516(12).16∴1457.1110= 5B1.1C165B1.1C16=112301.013045B11C5B11C5B1.1C16= 010110110001.000111002=2661.07082661070DEC.A16= D × 162+ E × 161+ C × 160+ A×16–1= 3328 + 224 + 12 + 0.625 =3564.625101.4 (b)1.4 (c)1.4 (d)

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Unit 1 Solutions81.12 (c)A52.A411= 10 × 121 + 5 × 11 + 2 + 10/11 + 4/121= 1267.94109| 12670.949| 140r799| 15r5(8).469| 1r690r1(4).14∴A52.A411= 1267.9410= 1657.84279...1305.3751016| 13050.37516| 81r9165r1(6).000∴1305.37510= 519.60016=010100011001.01100000000025196001644.8751016| 16440.87516| 102r12166r6(14).000∴1644.87510= 66C.E0016=011001101100.111000000000266CE001.10 (a)1.10 (c)1.5 (a)1111111(Add)+1010110011111(Sub)−101001011111(Multiply)×101000001111111100000011110111110010110See FLD p. 730 for solutions.101 111 010 100.1012= 5724.58= 5 × 83+ 7 × 82+ 2 × 81+ 4 × 80+ 5 × 8–1= 5 × 512 + 7 × 64 + 2 × 8 + 4 + 5/8= 3028.625101011 1101 0100.10102= BD4.A16B × 162+ D × 161+ 4 × 160+ A × 16–111 × 256 + 13 × 16 + 4 + 10/16= 3028.625101.11 (a)375.548= 3 × 64+ 7 × 8 + 5 + 5/8 + 4/64= 253.6875103| 2530.693| 84r133| 28r0(2).073| 9r133| 3r0(0).213| 1r030r1(0).633(1).89∴375.548= 100101.20013301.121016| 3010.1216| 18r13161r2(1).9216(14).72∴301.1210= 12D.1E16=000100101101.00011110212D1E11.331016| 1110.336r15 = F1616(5).2816(4).48∴111.3310= 6F.5416=01101111.0101010026F54100 001 101 111.0102= 4157.28= 4 × 83+ 1 × 825 × 81+ 7 × 80+ 2 × 8–1= 4 × 512 + 1 × 64 + 5 × 8 + 7 + 2/8= 2159.25101000 0110 1111.01002= 86F.416= 8 × 162+ 6 × 161+ F × 160× 4 × 16–1= 8 × 256 + 6 × 16 + 15 + 4/16= 2159.2510384.74104| 3840.744| 96r044| 24r0(2).964| 6r044| 1r2(3).840r14(3).36∴384.7410= 12000.2331134...1.12 (a)1.6, 1.7,1.8, 1.91.5 (b, c)See FLD p. 730 for solutions.1.10 (b)1.10 (d)1.11 (b)1.12 (b)

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Unit 1 Solutions93| 97.73|32r133|10r2(2).13|3r133|1r0(0).30r13(0).93(2).7∴97.710= 10121.2002....31110212.20211301 11 02 12.20 21 10 = 1425.6739Base 3Base 9000011022103114125206217228544.19= 5 × 92+ 4 × 91+ 4 × 90+ 1 × 9–1= 5 × 81 + 4 × 9 + 4 + 1/9= 445 1/91016| 4451/916| 27r131616| 1r11(1)7/90r116(12)4/916(7)1/9∴544.19= 1BD.1C716= 1 1011 1101.0001 1100 01112...1.131.15(c)16| 97.716| 6r1160r6(11).216(3).2∴97.710= 61.B3333....16(a) 61.B3333..16= 110 0001.1011 0011 0011 0011 0011...2(b) 1 100 001.101 100 110 011 001 100 11...2= 141.5 4631 4631....81.14 (a),(b), (c)1.14 (d)5| 97.75|19r255|3r4(3).50r35(2).5∴97.710= 342.322..51.14 (e)2983 63/6410=8| 29830.9848| 372r788| 46r4(7).8729| 5r680r5(6).976∴2983 63/6410= 5647.768(or 5647.778)= 101 110 100 111.111 1102(or 101 110 100 111.111 1112)1.16 (a)93.70108| 930.708| 11r588| 1r3(5).600r18(4).80∴93.7010= 135.548= 001 011 101.101 10021.16 (b)1900 31/32108| 19000.9698| 273r488| 29r5(7).7529| 3r580r3(6).016∴1900 31/3210= 3554.768= 011 101 101 100.111 1102109.30108| 1090.308| 13r588| 1r5(2).400r18(3).20∴109.3010= 155.238= 001 101 101.010 01121.16 (c)1.16 (d)

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Unit 1 Solutions1011011Quotient1110)1100000011110101001110110001110101011110111 Remainder11111110010(Add)110010(Sub)1110111101100111110101110010(Mult)1110111001000000001100101100101111101011001010100010101100101011010101011111(a)10100100(b)10010011011100110101100101100010011101011(c)11110011100111100101010110111Quotient110)1000110111010111101010110100111011 Remainder1.17(c)101110Quotient101)111010011011001101100010111010111 Remainder1100Quotient1001)1110010100110101001110 Remainder1 1 11 1 11111(Add)1111(Subtract)100110011100001101111(Multiply)10011111000001111000000111111111000011111 11 11101001(Add)1101001(Sub)110110110110100111111100111101001(Mult)110110000000011010011101001011010011001110110000000010011101101101001100100000110110100110110001001101.17 (a)1.17 (b)1.181.19(a)1.19(b)1.19(c)1.20(a)

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Unit 1 Solutions11(a) 4 + 3 is 10 in base 7, i.e., the sum digit is0 with a carry of 1 to the next column. 1 + 5 +4 is 10 in base 7. 1 + 6 + 0 is 10 in base 7. Thisoverflows since the correct sum is 10007.(b) 4 + 3 + 3 + 3 = 13 in base 10 and 23 in base5. Try base 10. 1 + 2 + 4 + 1 + 3 = 11 in base 10 sobase 10 does not produce a sum digit of 2. Try base5. 2 + 2 + 4 + 1 + 3 = 22 in base 5 so base 5 works.(c) 4 + 3 + 3 + 3 = 31 in base 4, 21 in base 6,and 11 in base 12. Try base 12. 1 + 2 + 4 + 1 + 3 =B in base 12 so base 12 does not work. Try base 4.3 + 2 + 4 + 1 + 3 = 31 in base 4 so base 4 does notwork. Try base 6. 2 + 2 + 4 + 1 + 3 = 20 so base 6is correct.1.21If the binary number has n bits (to the right of theradix point), then its precision is (1/2n+1). So tohave the same precision, n must satisfy(1/2n+1) < (1/2)(1/104) or n > 4/(log 2) = 13.28 so nmust be 14.1.22.363636....= (36/102)(1 + 1/102+ 1/104+ 1/106+ …)= (36/102)[1/(1 – 1/102)] = (36/102)[102/99]= 36/99 = 4/118(4/11) = 2 + 10/118(10/11) = 7 + 3/118(3/11) = 2 + 2/118(2/11) = 1 + 5/118(5/11) =3 + 7/118(7/11) = 5+ 1/118(1/11) = 0 + 8/118(8/11) = 5 + 9/118(9/11) = 6 + 6/118(6/11) = 4 + 4/118(4/11) = 2 + 10/11Repeats: .27213505642…….1.23Expand the base b number into a power seriesN = d3k-1b3k-1+ d3k-2b3k-2+ d3k-3b3k-3+ ….+d5b5+ d4b4+ d3b3+ d2b2+ d1b1+ d0b0+ d-1b-1+d-2b-2+ d-3b-3+ …. + d-3m+2b-3m+2+ d-3m+1b-3m+1+ d-3mb-3mwhere each dihas a value from 0 to(b-1). (Note that 0’s can be appended to the numberso that it has a multiple of 3 digits to the left andright of the radix point.) Factor b3from each groupof 3 consecutive digits of the number to obtainN = (d3k-1b2+ d3k-2b1+ d3k-3b0)(b3)(k-1)+ ….+ (d5b2+ d4b1+ d3b0)(b3)1+ (d2b2+ d1b1+d0b0)(b3)0+ (d-1b2+ d-2b1+ d-3b0)(b3)-1+ …. +(d-3m+2b2+ d-3m+1b1+ d-3mb0)(b3)-mEach (d3i-1b2+ d3i-2b1+ d3i-3b0) has a value from0 to [(b-1)b2+ (b-1)b1+ (b-1)b0]= (b-1)( b2+ b1+ b0) = (b3-1)so it is a valid digit in a base b3number.Consequently, the last expression is the powerseries expansion for a base b3number.1.24 (a)Expand the base b3number into a power seriesN = dk(b3)k+ dk-1(b3)k-1+ … + d1(b3)1+ d0(b3)0+ d-1(b3)-1+ …. + d-m(b3)-mwhere each dihas a value from 0 to (b3-1).Consequently, dican be represented as a base bnumber in the form(e3i-1b2+ e3i-2b1+ e3i-3b0)Where each ejhas a value from 0 to (b-1).Substituting these expressions for the diproduces apower series expansion for a base b number.1.24 (b)1011Quotient1010)11101001010100101010100001010110 Remainder100011Quotient1011)11000001110111000110111101101110 Remainder1.20(b)1.20(c)(5 - 1) = 45, (52- 1) = 445and (53- 1) = 4445(bn-1) = (b - 1)(bn-1) + bn-1= (b - 1)bn-1+ (b - 1)bn-2+ bn-2= (b - 1)bn-1+ (b - 1)bn-2+ …+ (b - 1)b + (b - 1)This expression is the polynomial expansion for thebase b number with n digits (b - 1)(b - 1) … (b - 1)1.25(a)1.25(b)1.26(a)(b + 1)2= b2+ 2b + 1 so (11b)2= 121bif b > 2.(b2+ b + 1)2= b4+ 2b3+ 3b2+ 2b + 1 so(111b)2= 12321bif b > 3.(b2+ 2b + 1)2= b4+ 4b3+ 6b2+ 4b + 1 so(121b)2= 14641bif b > 6.(b3+ b2+ b + 1)2= b6+ 2b5+ 3b4+ 4b3+ 3b2+2b + 1 so (1111b)2= 1234321bif b > 4.1.26(b)1.26(c)1.26(d)

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Solution Manual For Fundamentals of Logic Design, 7th Edition - Page 16 preview image

Unit 1 Solutions12AlternateSolutions:6221000001000120010300114011050111610007100181010910111100 0011 = 83(0100)(0101)(1100)(1101)AlternateSolutions:5221000001000120010300114011051000610017101081011911101110 0110 = 94(0100)(0101)(1100)(1101)1.311.32AlternateSolutions:732100000100012001030100401015011060111710008100191010A1100B1101(0011)(1011)1.33B4A9 = 1101 0101 1100 1010Alt.:=""1011"(a)84-2-100000101112011030101401005101161010710018100091111(b)The 9’scomplementof a decimalnumberrepresentedwith thisweighted codecan be obtainedby replacing0's with 1'sand 1's with0's (bit-by-bitcomplement).1.344321000001000120010301004100051001610107110081101911109154 =1110 0001 1001 10001.285-3-1-1 is possible, but6-4-1-1 is not, becausethere is no way torepresent 3 or 9.AlternateSolutions:5311000001000120011301004010151000610017101181100911015-4-1-1 is not possible, because there is no way torepresent 3 or 8. 6-3-2-1 is possible:6321000001000120010301004010150110610007100181010911001.291.30(0010)(0110)(1010)(1110)1.27(a)(0.12)3= (1/3 + 2/9)10= (2/6 + 8/36)10= (3/6 + 2/36)10= (0.32)6(0.375)10= (3/8)10= (0.3)8(a-1R-1+ a-2R-2+ ... + a-mR-m)Snwill be aninteger for every N only if Rmdivides Snforsome n. Hence, each factor of R must be a factorof S, not necessarily the same number of times.For a specific number N, (a-1R-1+ a-2R-2+ ...+ a-mR-m)Snwill be an integer if each factor ofRmis a factor of either Snor(a-1Rm-1+ a-2Rm-2+ ... + a-m)1.27(b)1.27(c)1.27(d)

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