HW4_Solution

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Page 1 of 17Homework 4 SolutionECE559:MOSVLSIDesign(Fall2009)ECEDepartment,PurdueUniversityAssigned: 15-Oct-2009Due: 22-Oct-2009Important:Pleaseturn-inallofyourcodesalongwiththewaveforms(whennecessary)duringsubmissionofyoursolution.Youmaybeaskedtoprovidethesoftcopyofyourcodesbyemailifsuchneedarises.Problem1:Consider a 2-input static CMOS based NAND gate. Derive a plot ofdelay-powertrade-offfor the gate. Clearly present your procedure withexplanationand state yourassumptions, if any. For delay estimation you should consider theworstcasedelayofagateand for power estimation you should consider thetime-averagedynamic power consumption.UseVDD= 2.5V, L = 300n,Input signal period = 10n with 50% duty cycle, Rise/Fall time = 0.5n, Delay time = 1n.Solution:A gate has worst case rising and falling delays depending on the applied input vectors. Both therising and falling delays are separately important as the critical path delay in a circuit isconcerned that depends on the signal transitions (depending on the logic functions of thegates) along a path.SPICECode* HW 4, Problem 1 Solution* ECE 559, Fall 2009, Purdue University.GLOBAL VDD!.lib "$CDK_DIR/models/hspice/public/publicModel/tsmc25N" NMOS.lib "$CDK_DIR/models/hspice/public/publicModel/tsmc25P" PMOS

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Homework 4 SolutionECE 559 (Fall 2009), Purdue UniversityPage 2 of 17.PARAM VDD = 2.5v.PARAM VREF = 'VDD/2'.PARAM L= 300n.PARAM WP= 900n.PARAM WN1 = 450n.PARAM WN2 = 450n* fanout of 4 is chosen.PARAM WPF = '8*WP'.PARAM WNF = '4*WN1'.PARAM RT= 0.5n.PARAM FT= 0.5n.PARAM DT= 1n.PARAM ST= 5n.TEMP25.OPTION POST.DATA data1WN1 WN2 WP450n450n450n450n450n525n450n450n600n450n450n675n450n450n750n450n450n825n450n450n900n450n450n975n* put all the set of data to be simulated.ENDDATAMP1 OUT IN1 VDD! VDD! TSMC25P L='L' W='WP'+AD='WP*2.5*L' AS='WP*2.5*L' PD='2*WP+5*L' PS='2*WP+5*L'+M=1

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Homework 4 SolutionECE 559 (Fall 2009), Purdue UniversityPage 3 of 17MP2 OUT IN2 VDD! VDD! TSMC25P L='L' W='WP'+AD='WP*2.5*L' AS='WP*2.5*L' PD='2*WP+5*L' PS='2*WP+5*L'+M=1MN1 OUT IN1 OUTX 0 TSMC25N L='L' W='WN1'+AD='WN1*2.5*L' AS='WN1*2.5*L' PD='2*WN1+5*L' PS='2*WN1+5*L'+M=1MN2 OUTX IN2 0 0 TSMC25N L='L' W='WN2'+AD='WN2*2.5*L' AS='WN2*2.5*L' PD='2*WN2+5*L' PS='2*WN2+5*L'+M=1MP3 OUT2 OUT VDD! VDD!TSMC25PL='L' W='WPF' AD='WPF*2.5*L' AS='WPF*2.5*L'PD='2*WPF+5*L' PS='2*WPF+5*L' M=1MN3OUT2OUT00TSMC25NL='L'W='WNF'AD='WNF*2.5*L'AS='WNF*2.5*L'PD='2*WNF+5*L' PS='2*WNF+5*L' M=1* set initial condition for 00->11 transition, VDD-Vtn.ic OUTX = 1.9882.TRAN 1n 'ST*103' START=0 uic SWEEP DATA=data1*.PRINT TRAN V(IN1) V(IN2) V(OUT) V(OUTX)* 011 & 010 sequences are added at the beginning to get the worst case delays* signal probability of 0.5 is assumed for both the inputsVIN1 IN1 0 PAT (VDD 0 DT RT FT STb0111000100010101010101000000000001010000010101010100010000010100010101010101000101000100010000000000010 r=0)VIN2 IN2 0 PAT (VDD 0 DT RT FT STb0101010001010100000101000001000100000101010000000000010000010100000000010101000000010001010001000001010 r=0)VVDD! VDD! 0 DC=VDD.MEASURE TRAN PROPAGATION_R+ TRIG v(IN2) VAL=VREF TD=DT FALL=1

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Homework 4 SolutionECE 559 (Fall 2009), Purdue UniversityPage 4 of 17+ TARG v(OUT) VAL=VREF TD=DT RISE=1.MEASURE TRAN PROPAGATION_F+ TRIG v(IN2) VAL=VREF TD=DT RISE=1+ TARG v(OUT) VAL=VREF TD=DT FALL=1.MEASURE TRAN MAX_PROPAGATION_DELAYPARAM='MAX(PROPAGATION_R,PROPAGATION_F)'.MEASURE TRAN AVG_POWER AVG POWER FROM=DT TO='ST*103'.ENDResultsThe minimum worst case propagation delay is found for WP=975nm, WN1=450nm, WN2=825nm.tplh=3.068e-10 sec, tphl=3.014e-10 sec, poweravg=1.825e-5 W.2.752.82.852.92.9533.053.13.153.2x 10-101.41.61.822.22.42.62.8 x 10-5Power Dissipation vs. Rising DelayPower Dissipation (W)Rising Delay (Sec)

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Homework 4 SolutionECE 559 (Fall 2009), Purdue UniversityPage 5 of 17In the figure above WN1=450nm, WN2=825nm and WPis varied between 825nm to 1650nm ininterval of 75nm. The values are chosen so that we don’t have any huge asymmetry in the risingand falling delays reducing the noise margin of operation for a circuit. The points show thetrade-off between delay and power as we see that if we have higher delay, we have lowerpower dissipation and vice-versa.2.72.752.82.852.92.9533.05x 10-101.81.922.12.22.32.4 x 10-5Power Dissipation vs. Falling DelayPower Dissipation (W)Falling Delay (Sec)In the figure above WP=975nm, WN2=825nm and WN1is varied between 450nm to 825nm ininterval of 75nm. The values are chosen so that we don’t have any huge asymmetry in the risingand falling delays reducing the noise margin of operation for a circuit. The points show thetrade-off between delay and power as we see that if we have higher delay, we have lowerpower dissipation and vice-versa.With the transistor widths and the rise/fall times given, we expect sharp changes in the transfercharacteristics and hence the short-circuit power dissipation can be ignored compared to thedynamic power consumption. Since we are using 300 nm technology library, the leakage poweralso can be considered small enough compared to the dynamic power consumption.

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Homework 4 SolutionECE 559 (Fall 2009), Purdue UniversityPage 6 of 17Problem2:Consider a 2-input static CMOS based NAND gate and adynamicNAND gate(precharge-evaluation based). Perform a SPICE simulation to calculate the dynamic powerconsumption for both. State your assumptions, if any andexplainyour results comparativelydiscussing if it meets your expectation or not. UseVDD= 2.5V, L = 300n,Wp = 900n, Wn = 450n (same Wp/Wn are also applicable for precharge/evaluate MOSs),Input/Clock signal period = 10n with 50% duty cycle, Rise/Fall time = 0.5n, Delay time = 1n,Signal probabilities: pA=1= 0.6, pB=1= 0.6 (A is the input closer to the output).Solution:For dynamic logic based NAND2 gate we have less output node capacitance than that of thestatic NAND2 gate as we have one less PMOS transistor connected at the output node. Alsosince we have less output node capacitance for dynamic logic based NAND2 gate, we alsoexpect it to drive less fanout gates’ input capacitances. Accordingly, we may think of expectingless switching power dissipation for dynamic NAND2 gate than that of the static NAND2 gate.However, for dynamic logic based gates, the signal transition probability at the output nodedoes not depend on the history of the inputs, but rather on the signal probabilities.For dynamic NAND2 gate, the switching activity,10,01,011*0.36dynamicdynamicoutABpppαα→→=======For static NAND2 gate, the switching activity()10,01,011111*** 1*0.2304staticstaticoutoutABABppppppαα→→=========−=Accordingly, the static NAND2 gate has quite lower switching activity than that of thecorresponding dynamic counterpart. The input signals are assumed to be uncorrelated.Based on the following discussion, we are not quite sure about the comparative nature of thepower dissipations for static and dynamic NAND2 gates.SPICECode(StaticNAND2Gate)* HW 4, Problem 2 Solution, static NAND2 gate* ECE 559, Fall 2009, Purdue University.GLOBAL VDD!

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