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    Page 1 of 17 Homework 4 Solution E C E 5 5 9 : M O S V L S I D e s i g n ( F a l l 2 0 0 9 ) E C E D e p a r t m e n t , P u r d u e U n i v e r s i t y Assigned: 15-Oct-2009 Due: 22-Oct-2009 I m p o r t a n t : P l e a s e t u r n - i n a l l o f y o u r c o d e s a l o n g w i t h t h e w a v e f o r m s ( w h e n n e c e s s a r y ) d u r i n g s u b m i s s i o n o f y o u r s o l u t i o n . Y o u m a y b e a s k e d t o p r o v i d e t h e s o f t c o p y o f y o u r c o d e s b y e m a i l i f s u c h n e e d a r i s e s . P r o b l e m 1 : Consider a 2-input static CMOS based NAND gate. Derive a plot of d e l a y - p o w e r t r a d e - o f f for the gate. Clearly present your procedure with e x p l a n a t i o n and state your assumptions, if any. For delay estimation you should consider the w o r s t c a s e d e l a y o f a g a t e and for power estimation you should consider the t i m e - a v e r a g e dynamic power consumption. Use V DD = 2.5V, L = 300n, Input signal period = 10n with 50% duty cycle, Rise/Fall time = 0.5n, Delay time = 1n. S o l u t i o n : A gate has worst case rising and falling delays depending on the applied input vectors. Both the rising and falling delays are separately important as the critical path delay in a circuit is concerned that depends on the signal transitions (depending on the logic functions of the gates) along a path. S P I C E C o d e * HW 4, Problem 1 Solution * ECE 559, Fall 2009, Purdue University .GLOBAL VDD! .lib "$CDK_DIR/models/hspice/public/publicModel/tsmc25N" NMOS .lib "$CDK_DIR/models/hspice/public/publicModel/tsmc25P" PMOS

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    Homework 4 Solution ECE 559 (Fall 2009), Purdue University Page 2 of 17 .PARAM VDD = 2.5v .PARAM VREF = 'VDD/2' .PARAM L = 300n .PARAM WP = 900n .PARAM WN1 = 450n .PARAM WN2 = 450n * fanout of 4 is chosen .PARAM WPF = '8*WP' .PARAM WNF = '4*WN1' .PARAM RT = 0.5n .PARAM FT = 0.5n .PARAM DT = 1n .PARAM ST = 5n .TEMP 25 .OPTION POST .DATA data1 WN1 WN2 WP 450n 450n 450n 450n 450n 525n 450n 450n 600n 450n 450n 675n 450n 450n 750n 450n 450n 825n 450n 450n 900n 450n 450n 975n * put all the set of data to be simulated .ENDDATA MP1 OUT IN1 VDD! VDD! TSMC25P L='L' W='WP' +AD='WP*2.5*L' AS='WP*2.5*L' PD='2*WP+5*L' PS='2*WP+5*L' +M=1

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    Homework 4 Solution ECE 559 (Fall 2009), Purdue University Page 3 of 17 MP2 OUT IN2 VDD! VDD! TSMC25P L='L' W='WP' +AD='WP*2.5*L' AS='WP*2.5*L' PD='2*WP+5*L' PS='2*WP+5*L' +M=1 MN1 OUT IN1 OUTX 0 TSMC25N L='L' W='WN1' +AD='WN1*2.5*L' AS='WN1*2.5*L' PD='2*WN1+5*L' PS='2*WN1+5*L' +M=1 MN2 OUTX IN2 0 0 TSMC25N L='L' W='WN2' +AD='WN2*2.5*L' AS='WN2*2.5*L' PD='2*WN2+5*L' PS='2*WN2+5*L' +M=1 MP3 OUT2 OUT VDD! VDD! TSMC25P L='L' W='WPF' AD='WPF*2.5*L' AS='WPF*2.5*L' PD='2*WPF+5*L' PS='2*WPF+5*L' M=1 MN3 OUT2 OUT 0 0 TSMC25N L='L' W='WNF' AD='WNF*2.5*L' AS='WNF*2.5*L' PD='2*WNF+5*L' PS='2*WNF+5*L' M=1 * set initial condition for 00->11 transition, VDD-Vtn .ic OUTX = 1.9882 .TRAN 1n 'ST*103' START=0 uic SWEEP DATA=data1 *.PRINT TRAN V(IN1) V(IN2) V(OUT) V(OUTX) * 011 & 010 sequences are added at the beginning to get the worst case delays * signal probability of 0.5 is assumed for both the inputs VIN1 IN1 0 PAT (VDD 0 DT RT FT ST b011100010001010101010100000000000101000001010101010001000001010001010101010 1000101000100010000000000010 r=0) VIN2 IN2 0 PAT (VDD 0 DT RT FT ST b010101000101010000010100000100010000010101000000000001000001010000000001010 1000000010001010001000001010 r=0) VVDD! VDD! 0 DC=VDD .MEASURE TRAN PROPAGATION_R + TRIG v(IN2) VAL=VREF TD=DT FALL=1

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    Homework 4 Solution ECE 559 (Fall 2009), Purdue University Page 4 of 17 + TARG v(OUT) VAL=VREF TD=DT RISE=1 .MEASURE TRAN PROPAGATION_F + TRIG v(IN2) VAL=VREF TD=DT RISE=1 + TARG v(OUT) VAL=VREF TD=DT FALL=1 .MEASURE TRAN MAX_PROPAGATION_DELAY PARAM='MAX(PROPAGATION_R,PROPAGATION_F)' .MEASURE TRAN AVG_POWER AVG POWER FROM=DT TO='ST*103' .END R e s u l t s The minimum worst case propagation delay is found for W P =975nm, W N1 =450nm, W N2 =825nm. t plh =3.068e-10 sec, t phl =3.014e-10 sec, power avg =1.825e-5 W. 2.75 2.8 2.85 2.9 2.95 3 3.05 3.1 3.15 3.2 x 10 -10 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 x 10 -5 Power Dissipation vs. Rising Delay Power Dissipation (W) Rising Delay (Sec)

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    Homework 4 Solution ECE 559 (Fall 2009), Purdue University Page 5 of 17 In the figure above W N1 =450nm, W N2 =825nm and W P is varied between 825nm to 1650nm in interval of 75nm. The values are chosen so that we don’t have any huge asymmetry in the rising and falling delays reducing the noise margin of operation for a circuit. The points show the trade-off between delay and power as we see that if we have higher delay, we have lower power dissipation and vice-versa. 2.7 2.75 2.8 2.85 2.9 2.95 3 3.05 x 10 -10 1.8 1.9 2 2.1 2.2 2.3 2.4 x 10 -5 Power Dissipation vs. Falling Delay Power Dissipation (W) Falling Delay (Sec) In the figure above W P =975nm, W N2 =825nm and W N1 is varied between 450nm to 825nm in interval of 75nm. The values are chosen so that we don’t have any huge asymmetry in the rising and falling delays reducing the noise margin of operation for a circuit. The points show the trade-off between delay and power as we see that if we have higher delay, we have lower power dissipation and vice-versa. With the transistor widths and the rise/fall times given, we expect sharp changes in the transfer characteristics and hence the short-circuit power dissipation can be ignored compared to the dynamic power consumption. Since we are using 300 nm technology library, the leakage power also can be considered small enough compared to the dynamic power consumption.

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    Homework 4 Solution ECE 559 (Fall 2009), Purdue University Page 6 of 17 P r o b l e m 2 : Consider a 2-input static CMOS based NAND gate and a d y n a m i c NAND gate (precharge-evaluation based). Perform a SPICE simulation to calculate the dynamic power consumption for both. State your assumptions, if any and e x p l a i n your results comparatively discussing if it meets your expectation or not. Use V DD = 2.5V, L = 300n, Wp = 900n, Wn = 450n (same Wp/Wn are also applicable for precharge/evaluate MOSs), Input/Clock signal period = 10n with 50% duty cycle, Rise/Fall time = 0.5n, Delay time = 1n, Signal probabilities: p A=1 = 0.6, p B=1 = 0.6 (A is the input closer to the output). S o l u t i o n : For dynamic logic based NAND2 gate we have less output node capacitance than that of the static NAND2 gate as we have one less PMOS transistor connected at the output node. Also since we have less output node capacitance for dynamic logic based NAND2 gate, we also expect it to drive less fanout gates’ input capacitances. Accordingly, we may think of expecting less switching power dissipation for dynamic NAND2 gate than that of the static NAND2 gate. However, for dynamic logic based gates, the signal transition probability at the output node does not depend on the history of the inputs, but rather on the signal probabilities. For dynamic NAND2 gate, the switching activity, 1 0, 0 1, 0 1 1 * 0.36 dynamic dynamic out A B p p p α α → → = = = = = = = For static NAND2 gate, the switching activity ( ) 1 0, 0 1, 0 1 1 1 1 1 * * * 1 * 0.2304 static static out out A B A B p p p p p p α α → → = = = = = = = = = − = Accordingly, the static NAND2 gate has quite lower switching activity than that of the corresponding dynamic counterpart. The input signals are assumed to be uncorrelated. Based on the following discussion, we are not quite sure about the comparative nature of the power dissipations for static and dynamic NAND2 gates. S P I C E C o d e ( S t a t i c N A N D 2 G a t e ) * HW 4, Problem 2 Solution, static NAND2 gate * ECE 559, Fall 2009, Purdue University .GLOBAL VDD!

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