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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Document preview page 1

Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 1

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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual

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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 1 preview image1SOLUTIONS MANUALPART 1: CHAPTERS 1-5Rev10/02/2018DIGITALDESIGNWITHANINTRODUCTIONtotheVERILOGHDL,VHDL, andSystemVerilogSixthEditionM. MORRIS MANOProfessorEmeritusCaliforniaStateUniversity,LosAngelesMICHAEL D. CILETTIProfessorEmeritusUniversityofColorado,ColoradoSpringsNote:SolutionstoproblemsrequiringHDLcodearepresentedinVerilogandVHDL
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 2 preview image
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 3 preview image.Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual.2CHAPTER 11.1Base-10:14 15 1617 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32Octal:16 17 2021 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40Hex:1011 12 13 14 15 16 17 18 19 1A1B1C1D1E1F 20Base-10:8910 11 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28Base-12 890A 0B 10 11 121314 15 16 17 18 19 1A 1B 20 21 2223241.2(a)32,768(b)67,108,864(c)6,871,947,6741.3(4310)5= 4 * 53+ 3 * 52+ 1 * 51= 58010(198)12= 1 * 122+ 9 * 121+ 8 * 120= 26010(445)8= 4 * 82+ 4 * 81+ 5 * 80= 29310(345)6= 3 * 62+ 4 * 61+ 5 * 60= 137101.416-bit binary: 1111_1111_1111_1111Decimal equivalent:216-1 = 65,53510Hexadecimal equivalent:FFFF161.5Let b = base(a)14/2 = (b + 4)/2 = 5, sob = 6(b)56/4 = (5*b + 6)/4 = 15 = 1*b + 5, so 5*b + 6 = 4*(1*b + 5) = 4*b + 20sob = 14(c)32 + 12 = 28, 3*b + 2 + 1*b + 2 = 2*b + 84*b + 4 = 2*b + 8, 2*b = 4, sob = 21.6(x – 3)(x – 6) = x2–(6 + 3)x + 6*3 = x2-11x + 22Therefore: 6 + 3 = b + 1, so b = 8Also,6*3 = (18)10= (22)81.764CD16= 0110_0100_1100_11012= 110_010_011_001 _101 = (62315 )8
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 4 preview image.Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual.31.8(a)Results of repeated division by 2 (quotients are followed by remainders):43110= 215(1);107(1);53(1);26(1);13(0);6(1)3(0)1(1)Answer:1111_10102= FA16(b)Results of repeated division by 16:43110= 26(15);1(10) (Faster)Answer: FA = 1111_10101.9(a)10110.01012= 16 + 4 + 2 + .25 + .0625 = 22.3125(b)16.516= 16 + 6 + 5*(.0615) = 22.3125(c)26.248= 2 * 8 + 6 + 2/8 + 4/64 = 22.3125(d)DABA.B16= 13*163+ 10*162+ 11*16 + 10 + 11/16 = 55,994.6875(e)1011.10012= 8 + 2 + 1 + .5 + .0625 = 11.56251.10(a)1.100102= 0001.10012= 1.916= 1 + 9/16 = 1.56310(b)110.0102= 0110.01002= 6.416= 6 + 4/16 = 6.2510Reason:110.0102is the same as1.100102shifted to the left by two places.1.111011.11101 | 111011.000010101001101100110110001010110The quotient is carried to two decimal places, giving 1011.11Checking:1110112/ 1012= 5910/ 510≅1011.112= 58.75101.12(a)10000 and 11011110111011
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 5 preview image.Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual.4x10110111011110111 = 5510+1010000 = 16101(b)62hand958h2Eh0010_11102Ehx34hB3882A9 5 8h= 239210+34h0011_010062h0110_0010 = 98101.13(a)Convert 27.315 to binary:IntegerRemainder CoefficientQuotient27/2 =13+½a0= 113/26+½a1= 16/23+0a2= 03/21+½a3= 1½0+½a4= 1
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 6 preview image.Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual.5........2710= 110112IntegerFraction Coefficient.315 x 2 =0+.630a-1= 0.630 x 2 =1+.26a-2= 1.26 x 2=0+.52a-3= 0.52 x 2=1+.04a-4= 1.31510≅.01012= .25 + .0625 = .312527.315≅11011.01012(b)2/3≅.6666666667IntegerFractionCoefficient6666_6666_67 x 2=1+.3333_3333_34a-1= 13333333334 x 2=0+.6666666668a-2= 06666666668 x 2=1+.3333333336a-3= 13333333336 x 2=0+.6666666672a-4= 06666666672 x 2=1+.3333333344a-5= 13333333344 x 2=0+.6666666688a-6= 06666666688 x 2=1+.3333333376a-7= 13333333376 x 2=0+.6666666752a-8= 0.666666666710≅.101010102= .5 + .125 + .0313 + ..0078 = .664110.101010102 = .1010_10102= .AA16= 10/16 + 10/256 = .664110(Same as (b)).1.14(a)1001_00001s comp:0110_11112s comp:0111_0001(b)0000_00001s comp:1111_11112s comp:0000_0000(c)1101_10101s comp:0010_01012s comp:0010_0110(d)1010_10111s comp:0101_01002s comp:0101_0111(e)1010_01011s comp:0101_10102s comp:0101_1011(f)`1111_11111s comp:0000_00002s comp:0000_00011.15(a)25,875,0369s comp:74,124,96310s comp:74,124,964(b)76,325,8009s comp:26,674,19910s comp:26,674,200(c)25,101,2369s comp:74,898,76310s comp:74,898,764(d)000000009s comp:9999999910s comp:1000000001.16C3AF:1100_0011_1010_11111s comp: 0011_1100_0101_00002s comp: 0011_1100_0101_0001 = 3C51C3AF15s comp:3C5016s comp:3C51
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 7 preview image.Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual.61.17(a)6,473 – 5297 = 11765297→05297→94702 (9s comp)→94703 (10s comp)6473 – 5297 = 6473 + 94703 = 101,176 (positive)Magnitude: 1,176Result: 6,473 – 5297 = 1176(b)1,076 – 3,217 = -2,1413,217→96,782 (9s comp)→96,783 (10s comp)1,076 – 3,217 = 1,076 + 96,783 = 97,858 (negative)Magnitude: 2,141Result: 1,076 – 3,217 = -2,141(c)4,361→04361→95638 (9s comp)→95639 (10s comp)2043 – 4361 = 02043 + 95639 = 97682 (Negative)Magnitude: 2318Result: 2043 – 6152 = -2318(d)745→00745→99254 (9s comp)→99255 (10s comp)1631 -745 = 01631 + 99255 = 0886 (Positive)Result: 1631 – 745 = 8861.18(a)0_10110(22)1s comp:1_010012s comp:1_01010Diff:result is negative0_10111(23)0_00001(Positive)Result: +1Check:23-22 = +1(b)0_1001101s comp:1_011001with sign extension2s comp:1_0110100_1000101_111100sign bit indicates that the0_0000111s complement0_000100 2s complement0_000100 magnitudeResult: -4Check: 34 -38 = -4(c)0_1101011s comp:1_0010102s comp:1_001011Diff:result is positive0_0010011_010100(negative)0_101011 (1s comp)0_101100(2s complement)101100 (magnitude)-4410(result)(d)0_0101011s comp:1_101010with sign extension2s comp:1_1010110_1010000_010011sign bit indicates that theResult:1910Check:40 – 21 = 1910
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 8 preview image71.19+9286→009286; +801→000801; -9286→990714; -801→999199(a)(+9286) + (_801) = 009286 + 000801 = 010087(b)(+9286) + (-801) = 009286 + 999199 = 008485(c)(-9286) + (+801) = 990714 + 000801 = 991515(d)(-9286) + (-801) = 990714 + 999199 = 9899131.20+49→0_110001 (Needs leading zero extension to indicate + value);+29→0_011101 (Leading 0 indicates + value)-49→1_001110 + 0_000001→1_001111-29→1_100011 (sign extension indicates negative value)(a)(+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.)Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20(b)(-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value)(-29) + (+49) = +20(c)Must increase word size by 1 (sign extension) to accomodate overflow of values:(-29) + (-49) = 11_100011 + 11_001111 = 10_110010 (1 indicates negative result)Magnitude:01_001110 = 7810Result:(-29) + (-49) = -78101.21+9742→009742→990257 (9's comp)→990258 (10s) comp+641→000641→999358 (9's comp)→999359 (10s) comp(a)(+9742) + (+641)→010383(b)(+9742) + (-641)→009742 + 999359 = 009101Result: (+9742) + (-641) = 9101(c)-9742) + (+641) = 990258 + 000641 = 990899 (negative)Magnitude: 009101Result: (-9742) + (641) = -9101(d)(-9742) + (-641) = 990258 + 999359 = 989617 (Negative)Magnitude: 10383Result: (-9742) + (-641) = -103831.226,514BCD:0110_0101_0001_0100.DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 9 preview imageASCII:0_011_0110__0_011_0101__1_011_0001__1_011_0100ASCII:0011_0110__0011_0101__1011_0001__1011_01003,274BCD:0011_0010_0111_0100ASCII:0011_0011_1011_0010_1011_0111_1011_01001.23011110010001 ( 791)011001011000 (+658)1101 111010010110 01100001 001101000001000100010100 01001001 (1,449)1.24(a)See text(b)6421Decimal0000000011001020011301004010150110601117101081011981.25(a)6,42810BCD:0110_0100_0010_1000(b)Excess-3:1001_0111_0101_1011(c)2421:1100_0100_0010_11102421:0110_0100_1000_1110(d)6311:1000_0110_0010_10111.26.DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.6,428 9s Comp:3,57164282421 code: 0011_1011_0111_00011.25(c):1100_0100_0010_1110 (2421 code – alternative #1)1s comp:0011_1011_1101_0001 (2421 code - alternative #2)6428
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 10 preview image6,42824210110_0100_1000_1110(2421 code alternative #2)1s comp1001_1011_0111_0001Match5,736 9s Comp:4,2632421 code: 0100_0010_1100_00111s comp:1011_1101_0011_110091.27For a deck with 52 cards, we need 6 bits (25= 32 < 52 < 64 = 26). Let the msb's selectthe suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and11. The remaining four bits select the "number" of the card. Example: 0001 (ace)through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spadesmight be coded as 11_1010. (Note: only 52 out of 64 patterns are used.)1.28G(dot)(space)Boole11000111_11101111_01101000_01101110_00100000_11000100_11101111_111001011.29Steve Jobs1.3073 F4 E5 76 E5 4A EF 62 7373:0_111_0011sF4:1_111_0100tE5:1_110_0101e76:0_111_0110vE5:1_110_0101e4A:0_100_1010jEF:1_110_1111o62:0_110_0010b73:0_111_0011sEven parity1.3162 + 32 = 94 printing characters; 34 special characters1.32Complement bit 6 (from the right)1.33(a)897(b)564(c)871(d)2,1991.34ASCII for decimal digits with even parity:(0):00110000(1):10110001(2):10110010(3):00110011(4):10110100(5):00110101(6):00110110(7):10110111(8):10111000(9):00111001.DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 11 preview image10CHAPTER 22.1(a)x y zx + y + z(x + y + z)'x'y'z'x' y' z'0 0 00111110 0 11011000 1 01010100 1 11010001 0 01001101 0 11001001 1 01000101 1 1100000x y z(xyz)(xyz)'x'y'z'x' + y' + z'0 0 00111110 0 10111010 1 00110110 1 10110011 0 00101111 0 10101011 1 00100111 1 1100000(b)x y zx + yz(x + y)(x + z)(x + y)(x + z)0 0 000000 0 100100 1 001000 1 111111 0 011111 0 111111 1 011111 1 11111(c)x y zx(y + z)xyxzxy + xz0 0 000000 0 100000 1 000000 1 100001 0 000001 0 110111 1 011011 1 11111(c)x y zxy + zx + (y + z)(x + y)(x + y) + z0 0 0000000 0 1011010 1 0011110 1 1011111 0 0101111 0 1111111 1 0111111 1 111111(d)x y zyzx(yz)xy(xy)z0 0 000000 0 100000 1 000000 1 110001 0 000001 0 100001 1 000101 1 111112.2(a)xy + xy' = x(y + y') = x(b)(x + y)(x + y') = x + yy' = x(x +y') + y(x + y') = xx + xy' + xy + yy' = x(c)xyz + x'y + xyz' = xy(z + z') + x'y = xy + x'y = y(d)(x + y)'(x' + y')' = (x'y')(xy) = (x'y')(yx) = x'(y'y)x = 0(e)(a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c'c = ac + bc +a'b'c'.DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 12 preview image11(f)a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c') = a'b + ab = (a' + a)b = b2.3(a)xyz + x'y + xyz' = xy + x'y = y(b)x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y)(c)(x + y)'(x' + y') = x'y'(x' + y') = x'y'(d)xy + x(wz + wz') = x(y +wz + wz') = x(w + y)(e)(yz' + x'w)(xy' + zw') = yz'xy' + yz'zw' + x'wxy' + x'wzw' = 0(f)(x' + z')(x + y' + z') = x'x + x'y' + x'z' + z'x + z'y' + z'z' = x'y' + x'z' + xz' + y'z' = z'+ y'(x' + z')= z' + y'z' + x'y' = z' + x'y'2.4(a)A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C'(b)(B'C' + D)' + D + BC + AD = (B'C')'D' + D + BC + AD =[(B + C)D' + D] + BC+ AD ==(D + D')(D + B + C) + BC + AD = D + AD + B + BC + C = D(1 + A) + B(1 +C) + C= B + C + D(c)A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD)= B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B(d)(A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D)= AA' + A'B + A'C'D = A'(B + C'D)(e)ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD2.5(a)xyFFsimplified(b).DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 13 preview image12xyFFsimplified(c)xyzFsimplifiedF(d)AB0FFsimplified(e).DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.xyzFsimplifiedF(f)
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 14 preview image13xyzFFsimplified2.6(a)ABCFFsimplified(b)xyzFFsimplified(c)xyFFsimplified.DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 15 preview image14.DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.
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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual - Page 16 preview image15(d)wxyzFsimplifiedF(e)ABCDFsimplified= 0F(f)wxyzFsimplifiedF2.7(a).DigitalDesignWithAnIntroductiontotheVerilogHDL,VHDL,andSystemVerilog, SixthEdition–SolutionManual.
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