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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual

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    1 SOLUTIONS MANUAL PART 1: CHAPTERS 1-5 Rev 10/02/2018 DIGITAL DESIGN WITH AN INTRODUCTION to the VERILOG HDL, VHDL, and SystemVerilog Sixth Edition M. MORRIS MANO Professor Emeritus California State University, Los Angeles MICHAEL D. CILETTI Professor Emeritus University of Colorado, Colorado Springs Note: Solutions to problems requiring HDL code are presented in Verilog and VHDL

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    .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual . 2 CHAPTER 1 1.1 Base-10: 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Octal: 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40 Hex: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Base-10: 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Base-12 8 9 0A 0B 10 11 12 13 14 15 16 17 18 19 1A 1B 20 21 22 23 24 1.2 (a) 32,768 (b) 67,108,864 (c) 6,871,947,674 1.3 (4310) 5 = 4 * 5 3 + 3 * 5 2 + 1 * 5 1 = 580 10 (198) 12 = 1 * 12 2 + 9 * 12 1 + 8 * 12 0 = 260 10 (445) 8 = 4 * 8 2 + 4 * 8 1 + 5 * 8 0 = 293 10 (345) 6 = 3 * 6 2 + 4 * 6 1 + 5 * 6 0 = 137 10 1.4 16-bit binary: 1111_1111_1111_1111 Decimal equivalent: 2 16 -1 = 65,535 10 Hexadecimal equivalent: FFFF 16 1.5 Let b = base (a) 14/2 = (b + 4)/2 = 5 , so b = 6 (b) 56/4 = (5*b + 6)/4 = 15 = 1*b + 5, so 5*b + 6 = 4*(1*b + 5) = 4*b + 20 so b = 14 (c) 32 + 12 = 28, 3*b + 2 + 1*b + 2 = 2*b + 8 4*b + 4 = 2*b + 8, 2*b = 4 , so b = 2 1.6 (x – 3)(x – 6) = x 2 –(6 + 3)x + 6*3 = x 2 -11x + 22 Therefore: 6 + 3 = b + 1, so b = 8 Also, 6*3 = (18) 10 = (22) 8 1.7 64CD 16 = 0110_0100_1100_1101 2 = 110_010_011_001 _101 = (62315 ) 8

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    .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual . 3 1.8 (a) Results of repeated division by 2 (quotients are followed by remainders): 431 10 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) 3(0) 1(1) Answer: 1111_1010 2 = FA 16 (b) Results of repeated division by 16: 431 10 = 26(15); 1(10) (Faster) Answer: FA = 1111_1010 1.9 (a) 10110.0101 2 = 16 + 4 + 2 + .25 + .0625 = 22.3125 (b) 16.5 16 = 16 + 6 + 5*(.0615) = 22.3125 (c) 26.24 8 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125 (d) DABA.B 16 = 13*16 3 + 10*16 2 + 11*16 + 10 + 11/16 = 55,994.6875 (e) 1011.1001 2 = 8 + 2 + 1 + .5 + .0625 = 11.5625 1.10 (a) 1.10010 2 = 0001.1001 2 = 1.9 16 = 1 + 9/16 = 1.563 10 (b) 110.010 2 = 0110.0100 2 = 6.4 16 = 6 + 4/16 = 6.25 10 Reason: 110.010 2 is the same as 1.10010 2 shifted to the left by two places. 1.11 1011.11 101 | 111011.0000 101 01001 101 1001 101 1000 101 0110 The quotient is carried to two decimal places, giving 1011.11 Checking: 111011 2 / 101 2 = 59 10 / 5 10 ≅ 1011.11 2 = 58.75 10 1.12 (a) 10000 and 110111 1011 1011

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    .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual . 4 x101 1011 1011 110111 = 55 10 +101 0000 = 16 10 1 (b) 62 h and 958 h 2E h 0010_1110 2E h x34h B 3 8 8 2 A 9 5 8 h = 2392 10 +34 h 0011_0100 62h 0110_0010 = 98 10 1.13 (a) Convert 27.315 to binary: Integer Remainder Coefficient Quotient 27/2 = 13 + ½ a 0 = 1 13/2 6 + ½ a 1 = 1 6/2 3 + 0 a 2 = 0 3/2 1 + ½ a 3 = 1 ½ 0 + ½ a 4 = 1

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    .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual . 5 . . . . . . . . 27 10 = 11011 2 Integer Fraction Coefficient .315 x 2 = 0 + .630 a -1 = 0 .630 x 2 = 1 + .26 a -2 = 1 .26 x 2 = 0 + .52 a -3 = 0 .52 x 2 = 1 + .04 a -4 = 1 .315 10 ≅ .0101 2 = .25 + .0625 = .3125 27.315 ≅ 11011.0101 2 (b) 2/3 ≅ .6666666667 Integer Fraction Coefficient 6666_6666_67 x 2 = 1 + .3333_3333_34 a -1 = 1 3333333334 x 2 = 0 + .6666666668 a -2 = 0 6666666668 x 2 = 1 + .3333333336 a -3 = 1 3333333336 x 2 = 0 + .6666666672 a -4 = 0 6666666672 x 2 = 1 + .3333333344 a -5 = 1 3333333344 x 2 = 0 + .6666666688 a -6 = 0 6666666688 x 2 = 1 + .3333333376 a -7 = 1 3333333376 x 2 = 0 + .6666666752 a -8 = 0 .6666666667 10 ≅ .10101010 2 = .5 + .125 + .0313 + ..0078 = .6641 10 .101010102 = .1010_1010 2 = .AA 16 = 10/16 + 10/256 = .6641 10 (Same as (b)). 1.14 (a) 1001_0000 1s comp: 0110_1111 2s comp: 0111_0001 (b) 0000_0000 1s comp: 1111_1111 2s comp: 0000_0000 (c) 1101_1010 1s comp: 0010_0101 2s comp: 0010_0110 (d) 1010_1011 1s comp: 0101_0100 2s comp: 0101_0111 (e) 1010_0101 1s comp: 0101_1010 2s comp: 0101_1011 (f) ` 1111_1111 1s comp: 0000_0000 2s comp: 0000_0001 1.15 (a) 25,875,036 9s comp: 74,124,963 10s comp: 74,124,964 (b) 76,325,800 9s comp: 26,674,199 10s comp: 26,674,200 (c) 25,101,236 9s comp: 74,898,763 10s comp: 74,898,764 (d) 00000000 9s comp: 99999999 10s comp: 100000000 1.16 C3AF: 1100_0011_1010_1111 1s comp: 0011_1100_0101_0000 2s comp: 0011_1100_0101_0001 = 3C51 C3AF 15s comp: 3C50 16s comp: 3C51

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    .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual . 6 1.17 (a) 6,473 – 5297 = 1176 5297 → 05297 → 94702 (9s comp) → 94703 (10s comp) 6473 – 5297 = 6473 + 94703 = 101,176 (positive) Magnitude: 1,176 Result: 6,473 – 5297 = 1176 (b) 1,076 – 3,217 = -2,141 3,217 → 96,782 (9s comp) → 96,783 (10s comp) 1,076 – 3,217 = 1,076 + 96,783 = 97,858 (negative) Magnitude: 2,141 Result: 1,076 – 3,217 = -2,141 (c) 4,361 → 04361 → 95638 (9s comp) → 95639 (10s comp) 2043 – 4361 = 02043 + 95639 = 97682 (Negative) Magnitude: 2318 Result: 2043 – 6152 = -2318 (d) 745 → 00745 → 99254 (9s comp) → 99255 (10s comp) 1631 -745 = 01631 + 99255 = 0886 (Positive) Result: 1631 – 745 = 886 1.18 (a) 0_10110 (22) 1s comp: 1_01001 2s comp: 1_01010 Diff: result is negative 0_10111 (23) 0_00001 (Positive) Result: +1 Check: 23-22 = +1 ( b) 0_100110 1s comp: 1_011001 with sign extension 2s comp: 1_011010 0_100010 1_111100 sign bit indicates that the 0_000011 1s complement 0_000100 2s complement 0_000100 magnitude Result: -4 Check: 34 -38 = -4 (c) 0_110101 1s comp: 1_001010 2s comp: 1_001011 Diff: result is positive 0_001001 1_010100 (negative) 0_101011 (1s comp) 0_101100 (2s complement) 101100 (magnitude) -44 10 (result) ( d ) 0_010101 1s comp: 1_101010 with sign extension 2s comp: 1_101011 0_101000 0_010011 sign bit indicates that the Result: 19 10 Check: 40 – 21 = 19 10

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    7 1.19 +9286 → 009286; +801 → 000801; -9286 → 990714; -801 → 999199 (a) (+9286) + (_801) = 009286 + 000801 = 010087 (b) (+9286) + (-801) = 009286 + 999199 = 008485 (c) (-9286) + (+801) = 990714 + 000801 = 991515 (d) (-9286) + (-801) = 990714 + 999199 = 989913 1.20 +49 → 0_110001 (Needs leading zero extension to indicate + value); +29 → 0_011101 (Leading 0 indicates + value) -49 → 1_001110 + 0_000001 → 1_001111 -29 → 1_100011 (sign extension indicates negative value) (a) (+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.) Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20 (b) (-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value) (-29) + (+49) = +20 (c) Must increase word size by 1 (sign extension) to accomodate overflow of values: (-29) + (-49) = 11_100011 + 11_001111 = 10_110010 (1 indicates negative result) Magnitude: 01_001110 = 78 10 Result: (-29) + (-49) = -78 10 1.21 +9742 → 009742 → 990257 (9's comp) → 990258 (10s) comp +641 → 000641 → 999358 (9's comp) → 999359 (10s) comp (a) (+9742) + (+641) → 010383 (b) (+9742) + (-641) → 009742 + 999359 = 009101 Result: (+9742) + (-641) = 9101 (c) -9742) + (+641) = 990258 + 000641 = 990899 (negative) Magnitude: 009101 Result: (-9742) + (641) = -9101 (d) (-9742) + (-641) = 990258 + 999359 = 989617 (Negative) Magnitude: 10383 Result: (-9742) + (-641) = -10383 1.22 6,514 BCD : 0110_0101_0001_0100 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual .

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    ASCII: 0_011_0110__0_011_0101__1_011_0001__1_011_0100 ASCII: 0011_0110__0011_0101__1011_0001__1011_0100 3,274 BCD: 0011_0010_0111_0100 ASCII: 0011_0011_1011_0010_1011_0111_1011_0100 1.23 0111 1001 0001 ( 791) 0110 0101 1000 (+658) 1101 1110 1001 0110 0110 0001 0011 0100 0001 0001 0001 0100 0100 1001 (1,449) 1.24 (a) See text (b) 6 4 2 1 Decimal 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 1 0 8 1 0 1 1 9 8 1.25 (a) 6,428 10 BCD: 0110_0100_0010_1000 (b) Excess-3: 1001_0111_0101_1011 (c) 2421: 1100_0100_0010_1110 2421: 0110_0100_1000_1110 (d) 6311: 1000_0110_0010_1011 1.26 . Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual . 6,428 9s Comp: 3,571 6 4 2 8 2421 code: 0011_1011_0111_0001 1.25(c): 1100_0100_0010_1110 (2421 code – alternative #1) 1s comp: 0011_1011_1101_0001 (2421 code - alternative #2) 6 4 2 8

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    6,428 2421 0110_0100_1000_1110(2421 code alternative #2) 1s comp 1001_1011_0111_0001 Match 5,736 9s Comp: 4,263 2421 code: 0100_0010_1100_0011 1s comp: 1011_1101_0011_1100 9 1.27 For a deck with 52 cards, we need 6 bits ( 2 5 = 32 < 52 < 64 = 2 6 ). Let the msb's select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the "number" of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are used.) 1.28 G (dot) (space) B o o l e 11000111_11101111_01101000_01101110_00100000_11000100_11101111_11100101 1.29 Steve Jobs 1.30 73 F4 E5 76 E5 4A EF 62 73 73: 0_111_0011 s F4: 1_111_0100 t E5: 1_110_0101 e 76: 0_111_0110 v E5: 1_110_0101 e 4A: 0_100_1010 j EF: 1_110_1111 o 62: 0_110_0010 b 73: 0_111_0011 s Even parity 1.31 62 + 32 = 94 printing characters; 34 special characters 1.32 Complement bit 6 (from the right) 1.33 (a) 897 (b) 564 (c) 871 (d) 2,199 1.34 ASCII for decimal digits with even parity: (0): 00110000 (1): 10110001 (2): 10110010 (3): 00110011 (4): 10110100 (5): 00110101 (6): 00110110 (7): 10110111 (8): 10111000 (9): 00111001 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual .

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    10 CHAPTER 2 2.1 (a) x y z x + y + z (x + y + z)' x' y' z' x' y' z' 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 x y z (xyz) (xyz)' x' y' z' x' + y' + z' 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 (b) x y z x + yz (x + y) (x + z) (x + y)(x + z) 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 (c) x y z x(y + z) xy xz xy + xz 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 (c) x y z x y + z x + (y + z) (x + y) (x + y) + z 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 (d) x y z yz x(yz) xy (xy)z 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 2.2 (a) xy + xy' = x(y + y') = x (b) (x + y)(x + y') = x + yy' = x(x +y') + y(x + y') = xx + xy' + xy + yy' = x (c) xyz + x'y + xyz' = xy(z + z') + x'y = xy + x'y = y (d) (x + y)'(x' + y')' = (x'y')(xy) = (x'y')(yx) = x'(y'y)x = 0 (e) (a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c'c = ac + bc +a'b'c' .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual .

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    11 (f) a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c') = a'b + ab = (a' + a)b = b 2.3 (a) xyz + x'y + xyz' = xy + x'y = y (b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y) (c) (x + y)'(x' + y') = x'y'(x' + y') = x'y' (d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y) (e) (yz' + x'w)(xy' + zw') = yz'xy' + yz'zw' + x'wxy' + x'wzw' = 0 (f) (x' + z')(x + y' + z') = x'x + x'y' + x'z' + z'x + z'y' + z'z' = x'y' + x'z' + xz' + y'z' = z' + y'(x' + z') = z' + y'z' + x'y' = z' + x'y' 2.4 (a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C' (b) (B'C' + D)' + D + BC + AD = (B'C')'D' + D + BC + AD =[(B + C)D' + D] + BC + AD = = (D + D')(D + B + C) + BC + AD = D + AD + B + BC + C = D(1 + A) + B(1 + C) + C = B + C + D (c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD) = B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B (d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D) = AA' + A'B + A'C'D = A'(B + C'D) (e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD 2.5 (a) x y F F simplified (b) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual .

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    12 x y F F simplified (c) x y z F simplified F (d) A B 0 F F simplified (e) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual . x y z F simplified F (f)

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    13 x y z F F simplified 2.6 (a) A B C F F simplified (b) x y z F F simplified (c) x y F F simplified .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual .

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    14 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual .

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    15 (d) w x y z F simplified F (e) A B C D F simplified = 0 F (f) w x y z F simplified F 2.7 (a) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual .

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